forked from M-Labs/artiq
fixes
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a20087848d
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cf48232a90
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@ -47,6 +47,9 @@ PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x71 servo coefficients + offset data
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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# 0x78 Miqro channel profile/window memories
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PHASER_ADDR_MIQRO_ADDR = 0x78
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PHASER_ADDR_MIQRO_DATA = 0x7a
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_TRF0 = 1 << 1
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@ -1280,3 +1283,59 @@ class Miqro:
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self.channel = channel
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self.base_addr = (self.channel.phaser.channel_base + 1 +
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self.channel.index) << 8
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@kernel
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def write8(self, addr, data):
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self.channel.phaser.write16(PHASER_ADDR_MIQRO_ADDR,
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(self.channel.index << 13) | addr)
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self.channel.phaser.write8(PHASER_ADDR_MIQRO_DATA,
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data)
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@kernel
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def write32(self, addr, data):
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for i in range(4):
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self.write8(addr + i, data >> (i * 8))
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@kernel
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def set_frequency_mu(self, oscillator, profile, ftw):
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self.write32((1 << 12) | (oscillator << 8) | (profile << 3), ftw)
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@kernel
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def set_amplitude_phase_mu(self, oscillator, profile, asf, pow=0):
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self.write32((1 << 12) | (oscillator << 8) | (profile << 3) | (1 << 2),
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(asf & 0xffff) | (pow << 16))
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@kernel
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def set_window(self, start, data, rate=1, shift=0, order=3, head=1, tail=1):
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if len(data) == 0 or len(data) >= (1 << 10):
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raise ValueError("invalid window length")
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if rate < 1 or rate > 1 << 12:
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raise ValueError("rate out of bounds")
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addr = start << 2
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self.write32(addr,
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((start + 1 + len(data)) & 0x3ff)
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| ((rate - 1) << 10)
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| (shift << 22)
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| (order << 28)
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| (head << 30)
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| (tail << 31)
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)
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for i in range(len(data)):
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addr += 4
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self.write32(addr, (data[i][0] & 0xffff) | (data[i][1] << 16))
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@kernel
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def pulse(self, window, profiles):
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data = [window, 0, 0]
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word = 0
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idx = 10
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for i in range(len(profiles)):
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if idx >= 30:
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word += 1
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idx = 0
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data[word] |= profiles[i] << (idx * 5)
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idx += 5
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while word >= 0:
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rtio_output(self.base_addr + word, data[word])
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delay_mu(8)
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word -= 1
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@ -123,7 +123,8 @@ def peripheral_fastino(module, peripheral, **kwargs):
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def peripheral_phaser(module, peripheral, **kwargs):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
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eem.Phaser.add_std(module, peripheral["ports"][0],
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peripheral.get("mode", "base"), **kwargs)
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def peripheral_hvamp(module, peripheral, **kwargs):
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@ -91,7 +91,7 @@ class Base(Module):
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class MiqroChannel(Module):
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def __init__(self, regs):
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def __init__(self):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=30, address_width=2, fine_ts_width=1,
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enable_replace=False))
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@ -100,7 +100,7 @@ class MiqroChannel(Module):
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regs = [Signal(30, reset_less=True) for _ in range(3)]
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dt = Signal(7, reset_less=True)
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stb = Signal()
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self.comb += self.pulase.payload.data.eq(Cat(stb, dt, regs))
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self.comb += self.pulse.eq(Cat(stb, dt, regs))
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self.sync.rtio += [
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dt.eq(dt + 2),
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If(self.ack,
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@ -145,8 +145,8 @@ class Miqro(Module):
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self.comb += [
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self.serializer.payload.eq(Cat(
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header.raw_bits(),
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self.ch0.pulse.payload,
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self.ch1.pulse.payload,
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self.ch0.pulse,
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self.ch1.pulse,
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)),
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self.ch0.ack.eq(self.serializer.stb),
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self.ch1.ack.eq(self.serializer.stb),
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