srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

gateware.test.suservo: Fix tests for python >=3.7

Browse Source 
Closes #1748
This commit is contained in:
Peter Drmota 2022-01-11 17:15:31 +08:00 committed by Sebastien Bourdeauducq
parent 9eee0e5a7b
commit 4eee49f889
3 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/test/suservo/test_adc.py
View File

@ -43,7 +43,7 @@ class TB(Module):
)
]
cnv_old = Signal(reset_less=True)
self.sync.async += [
self.sync.async_ += [
cnv_old.eq(self.cnv),
If(Cat(cnv_old, self.cnv) == 0b10,
sr.eq(Cat(reversed(self.data[2*i:2*i + 2]))),
@ -62,7 +62,7 @@ class TB(Module):
def _dly(self, sig, n=0):
n += self.params.t_rtt*4//2 # t_{sys,adc,ret}/t_async half rtt
dly = Signal(n, reset_less=True)
self.sync.async += dly.eq(Cat(sig, dly))
self.sync.async_ += dly.eq(Cat(sig, dly))
return dly[-1]
@ -85,8 +85,8 @@ def main():
assert not (yield dut.done)
while not (yield dut.done):
yield
x = (yield from [(yield d) for d in dut.data])
for i, ch in enumerate(x):
for i, d in enumerate(dut.data):
ch = yield d
assert ch == i, (hex(ch), hex(i))
run_simulation(tb, [run(tb)],
@ -95,7 +95,7 @@ def main():
"sys": (8, 0),
"adc": (8, 0),
"ret": (8, 0),
"async": (2, 0),
"async_": (2, 0),
},
)

6
artiq/gateware/test/suservo/test_dds.py
View File

@ -44,8 +44,10 @@ class TB(Module):
yield
dat = []
for dds in self.ddss:
v = yield from [(yield getattr(dds, k))
for k in "cmd ftw pow asf".split()]
v = []
for k in "cmd ftw pow asf".split():
f = yield getattr(dds, k)
v.append(f)
dat.append(v)
data.append((i, dat))
else:

2
artiq/gateware/test/suservo/test_servo.py
View File

@ -91,7 +91,7 @@ def main():
"sys": (8, 0),
"adc": (8, 0),
"ret": (8, 0),
"async": (2, 0),
"async_": (2, 0),
})