forked from M-Labs/artiq
parent
9eee0e5a7b
commit
4eee49f889
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@ -43,7 +43,7 @@ class TB(Module):
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)
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]
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cnv_old = Signal(reset_less=True)
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self.sync.async += [
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self.sync.async_ += [
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cnv_old.eq(self.cnv),
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If(Cat(cnv_old, self.cnv) == 0b10,
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sr.eq(Cat(reversed(self.data[2*i:2*i + 2]))),
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@ -62,7 +62,7 @@ class TB(Module):
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def _dly(self, sig, n=0):
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n += self.params.t_rtt*4//2 # t_{sys,adc,ret}/t_async half rtt
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dly = Signal(n, reset_less=True)
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self.sync.async += dly.eq(Cat(sig, dly))
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self.sync.async_ += dly.eq(Cat(sig, dly))
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return dly[-1]
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@ -85,8 +85,8 @@ def main():
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assert not (yield dut.done)
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while not (yield dut.done):
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yield
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x = (yield from [(yield d) for d in dut.data])
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for i, ch in enumerate(x):
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for i, d in enumerate(dut.data):
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ch = yield d
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assert ch == i, (hex(ch), hex(i))
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run_simulation(tb, [run(tb)],
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@ -95,7 +95,7 @@ def main():
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"sys": (8, 0),
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"adc": (8, 0),
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"ret": (8, 0),
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"async": (2, 0),
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"async_": (2, 0),
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},
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)
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@ -44,8 +44,10 @@ class TB(Module):
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yield
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dat = []
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for dds in self.ddss:
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v = yield from [(yield getattr(dds, k))
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for k in "cmd ftw pow asf".split()]
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v = []
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for k in "cmd ftw pow asf".split():
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f = yield getattr(dds, k)
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v.append(f)
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dat.append(v)
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data.append((i, dat))
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else:
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@ -91,7 +91,7 @@ def main():
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"sys": (8, 0),
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"adc": (8, 0),
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"ret": (8, 0),
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"async": (2, 0),
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"async_": (2, 0),
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})
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