forked from M-Labs/artiq
kernel_cpu: add fpu if not kasli v1.x
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@ -22,10 +22,10 @@ class KernelCPU(Module):
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self.cd_sys_kernel.clk.eq(ClockSignal()),
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self.cd_sys_kernel.rst.eq(self._reset.storage)
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]
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kasli_v1 = isinstance(platform, kasli.Platform) and platform.hw_rev in ("v1.0", "v1.1")
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self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
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vexriscv.VexRiscv(
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platform,
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exec_address))
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vexriscv.VexRiscv(platform, exec_address,
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variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G"))
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# DRAM access
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self.wb_sdram = wishbone.Interface()
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