forked from M-Labs/artiq
gateware: fix drtio/dma tests
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parent
02119282b8
commit
09945ecc4d
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@ -33,63 +33,67 @@ class Loopback(Module):
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class TB(Module):
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def __init__(self, nwords):
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def __init__(self, nwords, dw):
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self.submodules.link_layer = Loopback(nwords)
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self.submodules.aux_controller = ClockDomainsRenamer(
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{"rtio": "sys", "rtio_rx": "sys"})(DRTIOAuxController(self.link_layer))
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{"rtio": "sys", "rtio_rx": "sys"})(DRTIOAuxController(self.link_layer, dw))
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class TestAuxController(unittest.TestCase):
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def test_aux_controller(self):
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dut = TB(4)
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dut = {
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32: TB(4, 32),
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64: TB(4, 64)
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}
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def link_init():
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def link_init(dw):
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for i in range(8):
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yield
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yield dut.link_layer.ready.eq(1)
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yield dut[dw].link_layer.ready.eq(1)
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def send_packet(packet):
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def send_packet(packet, dw):
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for i, d in enumerate(packet):
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yield from dut.aux_controller.bus.write(i, d)
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yield from dut.aux_controller.transmitter.aux_tx_length.write(len(packet)*4)
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yield from dut.aux_controller.transmitter.aux_tx.write(1)
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yield from dut[dw].aux_controller.bus.write(i, d)
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yield from dut[dw].aux_controller.transmitter.aux_tx_length.write(len(packet)*dw//8)
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yield from dut[dw].aux_controller.transmitter.aux_tx.write(1)
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yield
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while (yield from dut.aux_controller.transmitter.aux_tx.read()):
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while (yield from dut[dw].aux_controller.transmitter.aux_tx.read()):
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yield
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def receive_packet():
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while not (yield from dut.aux_controller.receiver.aux_rx_present.read()):
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def receive_packet(dw):
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while not (yield from dut[dw].aux_controller.receiver.aux_rx_present.read()):
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yield
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length = yield from dut.aux_controller.receiver.aux_rx_length.read()
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length = yield from dut[dw].aux_controller.receiver.aux_rx_length.read()
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r = []
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for i in range(length//4):
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r.append((yield from dut.aux_controller.bus.read(256+i)))
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yield from dut.aux_controller.receiver.aux_rx_present.write(1)
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for i in range(length//(dw//8)):
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r.append((yield from dut[dw].aux_controller.bus.read(256+i)))
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yield from dut[dw].aux_controller.receiver.aux_rx_present.write(1)
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return r
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prng = random.Random(0)
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def send_and_check_packet():
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data = [prng.randrange(2**32-1) for _ in range(prng.randrange(1, 16))]
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yield from send_packet(data)
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received = yield from receive_packet()
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def send_and_check_packet(dw):
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data = [prng.randrange(2**dw-1) for _ in range(prng.randrange(1, 16))]
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yield from send_packet(data, dw)
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received = yield from receive_packet(dw)
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self.assertEqual(data, received)
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def sim():
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yield from link_init()
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def sim(dw):
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yield from link_init(dw)
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for i in range(8):
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yield from send_and_check_packet()
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yield from send_and_check_packet(dw)
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@passive
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def rt_traffic():
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def rt_traffic(dw):
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while True:
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while prng.randrange(4):
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yield
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yield dut.link_layer.tx_rt_frame.eq(1)
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yield dut[dw].link_layer.tx_rt_frame.eq(1)
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yield
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while prng.randrange(4):
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yield
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yield dut.link_layer.tx_rt_frame.eq(0)
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yield dut[dw].link_layer.tx_rt_frame.eq(0)
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yield
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run_simulation(dut, [sim(), rt_traffic()])
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run_simulation(dut[32], [sim(32), rt_traffic(32)])
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run_simulation(dut[64], [sim(64), rt_traffic(64)])
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@ -31,24 +31,25 @@ def encode_record(channel, timestamp, address, data):
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return encode_n(len(r)+1, 1, 1) + r
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def pack(x, size):
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def pack(x, size, dw):
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r = []
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for i in range((len(x)+size-1)//size):
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n = 0
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for j in range(i*size, (i+1)*size):
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n <<= 8
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for j in range(i*size//(dw//8), (i+1)*size//(dw//8)):
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n <<= dw
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try:
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n |= x[j]
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encoded = int.from_bytes(x[j*(dw//8): (j+1)*(dw//8)], "little")
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n |= encoded
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except IndexError:
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pass
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r.append(n)
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return r
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def encode_sequence(writes, ws):
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def encode_sequence(writes, ws, dw):
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sequence = [b for write in writes for b in encode_record(*write)]
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sequence.append(0)
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return pack(sequence, ws)
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return pack(sequence, ws, dw)
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def do_dma(dut, address):
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@ -84,9 +85,9 @@ prng = random.Random(0)
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class TB(Module):
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def __init__(self, ws):
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sequence1 = encode_sequence(test_writes1, ws)
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sequence2 = encode_sequence(test_writes2, ws)
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def __init__(self, ws, dw):
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sequence1 = encode_sequence(test_writes1, ws, dw)
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sequence2 = encode_sequence(test_writes2, ws, dw)
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offset = 512//ws
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assert len(sequence1) < offset
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sequence = (
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@ -97,7 +98,7 @@ class TB(Module):
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bus = wishbone.Interface(ws*8)
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self.submodules.memory = wishbone.SRAM(
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1024, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus)
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self.submodules.dut = dma.DMA(bus, dw)
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test_writes_full_stack = [
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@ -109,7 +110,7 @@ test_writes_full_stack = [
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class FullStackTB(Module):
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def __init__(self, ws):
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def __init__(self, ws, dw):
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self.ttl0 = Signal()
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self.ttl1 = Signal()
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@ -121,12 +122,12 @@ class FullStackTB(Module):
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rtio.Channel.from_phy(self.phy1)
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]
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sequence = encode_sequence(test_writes_full_stack, ws)
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sequence = encode_sequence(test_writes_full_stack, ws, dw)
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bus = wishbone.Interface(ws*8)
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bus = wishbone.Interface(ws*8, 32-log2_int(dw//8))
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self.submodules.memory = wishbone.SRAM(
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256, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus)
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self.submodules.dut = dma.DMA(bus, dw)
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self.submodules.tsc = rtio.TSC("async")
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self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
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self.comb += self.dut.cri.connect(self.rtio.cri)
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@ -134,16 +135,22 @@ class FullStackTB(Module):
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class TestDMA(unittest.TestCase):
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def test_dma_noerror(self):
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tb = TB(64)
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tb = {
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32: TB(64, 32),
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64: TB(64, 64)
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}
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def do_writes():
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yield from do_dma(tb.dut, 0)
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yield from do_dma(tb.dut, 512)
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def do_writes(dw):
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yield from do_dma(tb[dw].dut, 0)
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yield from do_dma(tb[dw].dut, 512)
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received = []
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received = {
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32: [],
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64: []
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}
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@passive
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def rtio_sim():
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dut_cri = tb.dut.cri
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def rtio_sim(dw):
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dut_cri = tb[dw].dut.cri
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while True:
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cmd = yield dut_cri.cmd
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if cmd == cri.commands["nop"]:
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@ -153,7 +160,7 @@ class TestDMA(unittest.TestCase):
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timestamp = yield dut_cri.o_timestamp
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address = yield dut_cri.o_address
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data = yield dut_cri.o_data
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received.append((channel, timestamp, address, data))
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received[dw].append((channel, timestamp, address, data))
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yield dut_cri.o_status.eq(1)
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for i in range(prng.randrange(10)):
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@ -163,32 +170,46 @@ class TestDMA(unittest.TestCase):
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self.fail("unexpected RTIO command")
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yield
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run_simulation(tb, [do_writes(), rtio_sim()])
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self.assertEqual(received, test_writes1 + test_writes2)
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run_simulation(tb[32], [do_writes(32), rtio_sim(32)])
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self.assertEqual(received[32], test_writes1 + test_writes2)
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run_simulation(tb[64], [do_writes(64), rtio_sim(64)])
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self.assertEqual(received[64], test_writes1 + test_writes2)
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def test_full_stack(self):
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tb = FullStackTB(64)
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tb = {
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32: FullStackTB(64, 32),
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64: FullStackTB(64, 64)
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}
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ttl_changes = []
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ttl_changes = {
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32: [],
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64: []
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}
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@passive
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def monitor():
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def monitor(dw):
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old_ttl_states = [0, 0]
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for time in itertools.count():
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ttl_states = [
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(yield tb.ttl0),
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(yield tb.ttl1)
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(yield tb[dw].ttl0),
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(yield tb[dw].ttl1)
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]
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for i, (old, new) in enumerate(zip(old_ttl_states, ttl_states)):
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if new != old:
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ttl_changes.append((time, i))
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ttl_changes[dw].append((time, i))
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old_ttl_states = ttl_states
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yield
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run_simulation(tb, {"sys": [
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do_dma(tb.dut, 0), monitor(),
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run_simulation(tb[32], {"sys": [
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do_dma(tb[32].dut, 0), monitor(32),
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(None for _ in range(70)),
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]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
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run_simulation(tb[64], {"sys": [
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do_dma(tb[64].dut, 0), monitor(64),
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(None for _ in range(70)),
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]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
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correct_changes = [(timestamp + 11, channel)
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for channel, timestamp, _, _ in test_writes_full_stack]
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self.assertEqual(ttl_changes, correct_changes)
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self.assertEqual(ttl_changes[32], correct_changes)
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self.assertEqual(ttl_changes[64], correct_changes)
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