forked from M-Labs/artiq
parent
bbac477092
commit
9d493028e5
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@ -26,7 +26,7 @@ class DDS(spi.SPISimple):
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self.profile = [Signal(32 + 16 + 16, reset_less=True)
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for i in range(params.channels)]
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cmd = Signal(8, reset=0x0e) # write to single tone profile 0
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cmd = Signal(8, reset=0x15) # write to single tone profile 7
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assert params.width == len(cmd) + len(self.profile[0])
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self.sync += [
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