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72f9f7ed79
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runtime: implement mailbox, use it for kernel startup, exceptions and termination
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2015-04-05 22:07:34 +08:00 |
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1bca614d11
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runtime: use UP/AMP terminology
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2015-04-05 17:55:05 +08:00 |
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ef375b5c9c
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pipistrello: add double-cpu
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2015-04-04 20:52:08 -06:00 |
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afc3982555
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pipistrello: refactor single-cpu
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2015-04-04 20:51:47 -06:00 |
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0ae4492077
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pipistrello: use mem_decoder
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2015-04-04 20:51:47 -06:00 |
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e50661dac4
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pipistrello: fix dcm parameters, move leds, fix names
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2015-04-04 20:51:47 -06:00 |
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cbdc1ba46f
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runtime: biprocessor support (incomplete, WIP)
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2015-04-04 22:08:32 +08:00 |
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277e038569
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targets/kc705: add LED on RTIO
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2015-04-04 22:07:23 +08:00 |
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21a0919ddc
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runtime: load support code into kernel CPU
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2015-04-03 17:44:56 +08:00 |
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c6d3750076
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runtime,amp: set kernel memory start to SDRAM+128K, use custom linker file to split memory
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2015-04-03 16:03:38 +08:00 |
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5f7161a7de
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kc705: 16 TTLs
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2015-04-03 15:57:25 +08:00 |
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Florent Kermarrec
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2995f0a705
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remove use of _r prefix on CSRs
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2015-04-02 18:30:44 +08:00 |
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88a1707ef9
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soc: use new location of gpio module
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2015-04-02 17:19:00 +08:00 |
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f124350555
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runtime: disable kernel-CPU functions when kernel-CPU not present
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2015-04-02 17:00:59 +08:00 |
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4b66e3108a
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runtime: demonstrate basic inter-CPU communication
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2015-04-02 16:54:08 +08:00 |
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5fd7f68f48
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targets/kc705: dual-CPU design
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2015-04-02 16:53:57 +08:00 |
|
Yann Sionneau
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e9092edb98
|
Remove one RTIO out channel to free up some space for travis builds to succeed
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2015-03-30 19:51:52 +08:00 |
|
Florent Kermarrec
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494c670cd2
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targets/artiq_ppro: use new sdram_controller_settings parameter
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2015-03-21 23:19:16 +01:00 |
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fdca0a71ff
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add ARTIQMidiSoC based on pipistrello
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2015-03-19 11:37:15 -06:00 |
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7a1d60ee15
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coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors
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2015-03-13 14:55:18 +01:00 |
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0416da8634
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runtime/test: implement ttlout, clksel and dds functions
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2015-03-12 13:14:06 +01:00 |
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3122623c6f
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rtio: make 63-bit timestamp counter the default [soc]
|
2015-03-12 13:13:35 +01:00 |
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d38014b07d
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soc/runtime: import DDS/TTL tester (functions not accessible yet)
|
2015-03-11 22:02:19 +01:00 |
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28bce9ee40
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artiqlib -> artiq.gateware
|
2015-03-08 11:00:24 +01:00 |
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15d09c0b94
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runtime: use new uart tuning word function
|
2015-03-02 23:36:05 +00:00 |
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|
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4e5320be28
|
Merge branch 'master' of https://github.com/m-labs/artiq
|
2015-02-28 07:34:38 -07:00 |
|
Florent Kermarrec
|
9cf8db2f14
|
adapt code to MiSoC's changes
|
2015-02-28 07:34:11 -07:00 |
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7028d85255
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targets/ppro: disable L2
|
2015-02-27 18:02:21 -07:00 |
|
Joe Britton
|
0127de9bb5
|
soc: add_cpu_csr_region -> add_csr_region
|
2015-02-27 15:02:28 -07:00 |
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|
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61f33a9a04
|
soc/ad9858: do not put code in __init__.py
|
2015-02-26 23:31:43 -07:00 |
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|
|
da917f768e
|
initial kc705 support
|
2015-02-26 21:50:52 -07:00 |
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|
|
f7232fd3d1
|
support exceptions raised by RPCs
|
2014-12-20 21:33:22 +08:00 |
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0d10ae7580
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rpc: support all data types as parameters
|
2014-12-19 12:46:24 +08:00 |
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059608d1fd
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dds: fix phase modes
|
2014-12-09 13:50:33 +08:00 |
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fc690ead75
|
runtime: support clock switching
|
2014-12-02 14:06:32 +08:00 |
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|
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94218f785e
|
comm_serial: cleanup
|
2014-12-02 11:09:02 +08:00 |
|
Yann Sionneau
|
20adb57140
|
comm_serial: allow to use dynamic baudrate
|
2014-12-02 10:42:14 +08:00 |
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|
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c591f1a74d
|
targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
|
2014-12-01 18:53:29 +08:00 |
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|
|
cd587e4f12
|
rtio: do housekeeping in gateware
|
2014-12-01 17:32:36 +08:00 |
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|
|
99d530e498
|
targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
|
2014-12-01 17:31:35 +08:00 |
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|
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50e0bf3280
|
rtio: optimize flag handling
|
2014-12-01 14:29:50 +08:00 |
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572eecc57b
|
rtio: stricter upper bound on guard time to avoid race condition
|
2014-12-01 14:27:03 +08:00 |
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|
|
7166ca82d1
|
targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
|
2014-11-30 22:31:55 +08:00 |
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|
|
1f6441948d
|
more TTL channels and larger input FIFOs on Papilio Pro
|
2014-11-30 15:50:57 +08:00 |
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e5286c57ab
|
rtio: fix input FIFO depth config
|
2014-11-30 12:12:35 +08:00 |
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bf745e53c9
|
rtio: register FIFO output to improve timing
|
2014-11-30 10:51:12 +08:00 |
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|
|
dda4002ae1
|
rtio/phy: fix input synchronization
|
2014-11-30 10:50:48 +08:00 |
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c78c5a2b4f
|
rtio: fix guard cycle computation
|
2014-11-30 01:00:52 +08:00 |
|
|
|
39c4b5416f
|
targets/ARTIQMiniSoC: 125MHz RTIO clocking
|
2014-11-30 01:00:27 +08:00 |
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9aafe89518
|
rtio: use Record
|
2014-11-30 00:59:39 +08:00 |
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