forked from M-Labs/artiq
rtio: register FIFO output to improve timing
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@ -62,8 +62,9 @@ class _RTIOCounter(Module):
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * FIFO latency: Tsys + 2*Tio
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# * FIFO buffer latency: Tio
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# Therefore we must choose:
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# guard_io_cycles > (3*Tio + 4*Tsys)/Tio
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# guard_io_cycles > (4*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached without checking the FIFO's writable status. If the FIFO is full,
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@ -144,16 +145,29 @@ class _RTIOBankO(Module):
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)
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]
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# FIFO read
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# Buffer output of FIFO to improve timing
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dout_stb = Signal()
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dout_ack = Signal()
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dout = Record(ev_layout)
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self.sync.rio += \
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If(fifo.re,
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dout_stb.eq(1),
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dout.eq(fifo.dout)
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).Elif(dout_ack,
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dout_stb.eq(0)
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)
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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# FIFO read through buffer
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter.o_value_rio)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter.o_value_rio),
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chif.o_stb.eq(dout_stb & dout_ack),
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chif.o_value.eq(dout.value)
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]
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if fine_ts_width:
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self.comb += chif.o_fine_ts.eq(
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fifo.dout.timestamp[:fine_ts_width])
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dout.timestamp[:fine_ts_width])
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self.comb += \
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self.writable.eq(Array(fifo.writable for fifo in fifos)[self.sel])
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