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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA

This commit is contained in:
Sebastien Bourdeauducq 2014-12-01 17:31:35 +08:00
parent 3a27f49bff
commit 99d530e498
3 changed files with 3 additions and 7 deletions
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6
doc/manual/fpga_board_ports.rst
View File

@ -32,11 +32,7 @@ When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in ad
+--------------+----------+-----------------+
| 7 | TTL5 | Output only |
+--------------+----------+-----------------+
| 8 | TTL6 | Output only |
+--------------+----------+-----------------+
| 9 | TTL7 | Output only |
+--------------+----------+-----------------+
| 10 | FUD | DDS driver only |
| 8 | FUD | DDS driver only |
+--------------+----------+-----------------+
The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Papilio Pro board), the corresponding pins on the Papilio Pro can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.

2
soc/runtime/rtio.c
View File

@ -95,7 +95,7 @@ int rtio_pileup_count(int channel)
return r;
}
#define RTIO_FUD_CHANNEL 10
#define RTIO_FUD_CHANNEL 8
void rtio_fud_sync(void)
{

2
soc/targets/artiq.py
View File

@ -92,7 +92,7 @@ class ARTIQMiniSoC(BaseSoC):
platform.request("ttl_h_tx_en").eq(1)
]
rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(8)] + [fud]
rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY(