forked from M-Labs/artiq
rtio: stricter upper bound on guard time to avoid race condition
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@ -67,22 +67,23 @@ class _RTIOCounter(Module):
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# guard_io_cycles > (4*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached without checking the FIFO's writable status. If the FIFO is full,
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# this will produce an overflow and the event will be incorrectly discarded.
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# reached. This can fill the FIFO and deassert the writable flag. A race
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# condition occurs that causes problems if the deassertion happens between
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# the CPU checking the writable flag (and reading 1) and writing a new event.
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#
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# When the FIFO is full, it contains fifo_depth events of strictly increasing
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# timestamps.
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# When the FIFO is about to be full, it contains fifo_depth-1 events of
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# strictly increasing timestamps.
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#
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# Thus the overflow-causing event's timestamp must satisfy:
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# timestamp*Tio > fifo_depth*Tio + time
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# Thus the FIFO-filling event's timestamp must satisfy:
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# timestamp*Tio > (fifo_depth-1)*Tio + time
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# We also have (guard time reached):
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# timestamp*Tio < time + guard_io_cycles*Tio
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# [NB: time > counter.o_value_sys*Tio]
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# Thus we must have:
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# guard_io_cycles > fifo_depth
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# guard_io_cycles > fifo_depth-1
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#
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# We can prevent overflows by choosing instead:
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# guard_io_cycles < fifo_depth
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# guard_io_cycles < fifo_depth-1
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth, guard_io_cycles):
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