forked from M-Labs/artiq
targets/kc705: dual-CPU design
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@ -4,9 +4,10 @@ from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from misoclib.soc import mem_decoder
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from targets.kc705 import BaseSoC
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from artiq.gateware import rtio, ad9858
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from artiq.gateware import amp, rtio, ad9858
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_tester_io = [
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@ -67,15 +68,14 @@ class _RTIOCRG(Module, AutoCSR):
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o_O=self.cd_rtio.clk)
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class ARTIQSoC(BaseSoC):
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class _ARTIQSoCPeripherals(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
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**kwargs):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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@ -100,14 +100,44 @@ class ARTIQSoC(BaseSoC):
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clk_freq=125000000,
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ififo_depth=512)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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self.comb += dds_pads.fud_n.eq(~fud)
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default_subtarget = ARTIQSoC
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class ARTIQSoCBasic(_ARTIQSoCPeripherals):
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def __init__(self, *args, **kwargs):
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_ARTIQSoCPeripherals.__init__(self, *args, **kwargs)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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class ARTIQSoC(_ARTIQSoCPeripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_ARTIQSoCPeripherals.csr_map)
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def __init__(self, platform, *args, **kwargs):
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_ARTIQSoCPeripherals.__init__(self, platform, *args, **kwargs)
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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default_subtarget = ARTIQSoCBasic
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