forked from M-Labs/artiq
pipistrello: add double-cpu
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@ -7,7 +7,7 @@ from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from targets.pipistrello import BaseSoC
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from artiq.gateware import rtio, ad9858
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from artiq.gateware import amp, rtio, ad9858
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_tester_io = [
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@ -140,4 +140,27 @@ class Single(_QcAdapterBase):
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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class Double(_QcAdapterBase):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_QcAdapterBase.csr_map)
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def __init__(self, platform, *args, **kwargs):
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_QcAdapterBase.__init__(self, platform, **kwargs)
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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default_subtarget = Single
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