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Merge branch 'master' of https://github.com/m-labs/artiq

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This commit is contained in:
Sebastien Bourdeauducq 2015-02-28 07:34:38 -07:00
commit 4e5320be28
2 changed files with 4 additions and 3 deletions
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2
soc/targets/artiq_kc705.py
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@ -103,7 +103,7 @@ class ARTIQSoC(BaseSoC):
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)

5
soc/targets/artiq_ppro.py
View File

@ -92,7 +92,8 @@ class ARTIQMiniSoC(BaseSoC):
}
csr_map.update(BaseSoC.csr_map)
def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
def __init__(self, platform, cpu_type="or1k",
ramcon_type="minicon", with_l2=False,
with_test_gen=False, **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, ramcon_type=ramcon_type,
@ -123,7 +124,7 @@ class ARTIQMiniSoC(BaseSoC):
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))