srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

rtio: fix input FIFO depth config

This commit is contained in:
Sebastien Bourdeauducq 2014-11-30 12:12:35 +08:00
parent bf745e53c9
commit e5286c57ab
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
soc/artiqlib/rtio/core.py
View File

@ -286,7 +286,7 @@ class RTIO(Module, AutoCSR):
self.submodules.bank_o = _RTIOBankO(
phy.rbus, self.counter, fine_ts_width, ofifo_depth, guard_io_cycles)
self.submodules.bank_i = _RTIOBankI(
phy.rbus, self.counter, fine_ts_width, ofifo_depth)
phy.rbus, self.counter, fine_ts_width, ififo_depth)
# CSRs
self._r_reset = CSRStorage(reset=1)