forked from M-Labs/artiq
pipistrello: fix dcm parameters, move leds, fix names
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d1653589f9
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e50661dac4
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@ -50,19 +50,19 @@ _tester_io = [
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]
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class _RTIOMiniCRG(Module, AutoCSR):
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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self._clock_sel = CSRStorage()
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self.clock_domains.cd_rtio = ClockDomain()
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# 80MHz -> 125MHz
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# 75MHz -> 125MHz
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rtio_internal_clk = Signal()
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self.specials += Instance("DCM_CLKGEN",
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p_CLKFXDV_DIVIDE=2,
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p_CLKFX_DIVIDE=16,
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p_CLKFX_DIVIDE=3,
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p_CLKFX_MD_MAX=1.6,
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p_CLKFX_MULTIPLY=25,
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p_CLKIN_PERIOD=12.5,
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p_CLKFX_MULTIPLY=5,
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p_CLKIN_PERIOD=1e3/75,
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p_SPREAD_SPECTRUM="NONE",
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p_STARTUP_WAIT="FALSE",
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i_CLKIN=ClockSignal(),
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@ -100,10 +100,6 @@ class ARTIQMidiSoC(BaseSoC):
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1),
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platform.request("user_led", 2),
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platform.request("user_led", 3),
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platform.request("user_led", 4),
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platform.request("ext_led", 0),
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))
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fud = Signal()
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@ -115,8 +111,10 @@ class ARTIQMidiSoC(BaseSoC):
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rtio_ins += [platform.request("xtrig", 0)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs += [fud]
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rtio_outs += [platform.request("ext_led", 0)]
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rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiocrg = _RTIOCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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rtio_ins + rtio_outs,
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output_only_pads=set(rtio_outs))
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