forked from M-Labs/artiq
artiqlib -> artiq.gateware
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from artiq.gateware.rtio import phy
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from artiq.gateware.rtio.core import RTIO
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@ -7,7 +7,7 @@ from migen.genlib.cdc import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from artiqlib.rtio.rbus import get_fine_ts_width
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from artiq.gateware.rtio.rbus import get_fine_ts_width
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class _GrayCodeTransfer(Module):
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from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from artiqlib.rtio.rbus import create_rbus
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from artiq.gateware.rtio.rbus import create_rbus
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class SimplePHY(Module):
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from artiqlib.rtio import phy
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from artiqlib.rtio.core import RTIO
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@ -6,7 +6,7 @@ from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from targets.kc705 import BaseSoC
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from artiqlib import rtio, ad9858
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from artiq.gateware import rtio, ad9858
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_tester_io = [
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@ -6,7 +6,7 @@ from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from targets.ppro import BaseSoC
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from artiqlib import rtio, ad9858
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from artiq.gateware import rtio, ad9858
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_tester_io = [
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