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artiqlib -> artiq.gateware

This commit is contained in:
Sebastien Bourdeauducq 2015-03-08 11:00:24 +01:00
parent 9fad01d967
commit 28bce9ee40
9 changed files with 6 additions and 6 deletions

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@ -0,0 +1,2 @@
from artiq.gateware.rtio import phy
from artiq.gateware.rtio.core import RTIO

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@ -7,7 +7,7 @@ from migen.genlib.cdc import *
from migen.genlib.fifo import AsyncFIFO
from migen.genlib.resetsync import AsyncResetSynchronizer
from artiqlib.rtio.rbus import get_fine_ts_width
from artiq.gateware.rtio.rbus import get_fine_ts_width
class _GrayCodeTransfer(Module):

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@ -1,7 +1,7 @@
from migen.fhdl.std import *
from migen.genlib.cdc import MultiReg
from artiqlib.rtio.rbus import create_rbus
from artiq.gateware.rtio.rbus import create_rbus
class SimplePHY(Module):

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@ -1,2 +0,0 @@
from artiqlib.rtio import phy
from artiqlib.rtio.core import RTIO

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@ -6,7 +6,7 @@ from mibuild.generic_platform import *
from misoclib.cpu.peripherals import gpio
from targets.kc705 import BaseSoC
from artiqlib import rtio, ad9858
from artiq.gateware import rtio, ad9858
_tester_io = [

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@ -6,7 +6,7 @@ from mibuild.generic_platform import *
from misoclib.cpu.peripherals import gpio
from targets.ppro import BaseSoC
from artiqlib import rtio, ad9858
from artiq.gateware import rtio, ad9858
_tester_io = [