Sebastien Bourdeauducq 572eecc57b rtio: stricter upper bound on guard time to avoid race condition		2014-12-01 14:27:03 +08:00
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artiqlib	rtio: stricter upper bound on guard time to avoid race condition	2014-12-01 14:27:03 +08:00
runtime	more TTL channels and larger input FIFOs on Papilio Pro	2014-11-30 15:50:57 +08:00
targets	targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)	2014-11-30 22:31:55 +08:00