Sebastien Bourdeauducq 7166ca82d1 targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)		2014-11-30 22:31:55 +08:00
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artiqlib	rtio: fix input FIFO depth config	2014-11-30 12:12:35 +08:00
runtime	more TTL channels and larger input FIFOs on Papilio Pro	2014-11-30 15:50:57 +08:00
targets	targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)	2014-11-30 22:31:55 +08:00