forked from M-Labs/artiq
rtio: fix guard cycle computation
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@ -61,10 +61,9 @@ class _RTIOCounter(Module):
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * guard time detection latency: Tsys
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# * FIFO latency: Tsys + 2*Tio
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# Therefore we must choose:
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# guard_io_cycles > (3*Tio + 5*Tsys)/Tio
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# guard_io_cycles > (3*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached without checking the FIFO's writable status. If the FIFO is full,
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