forked from M-Labs/artiq
targets/artiq_ppro: use new sdram_controller_settings parameter
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@ -4,6 +4,7 @@ from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.cpu.peripherals import gpio
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.ppro import BaseSoC
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from artiq.gateware import rtio, ad9858
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@ -93,11 +94,10 @@ class ARTIQMiniSoC(BaseSoC):
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k",
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ramcon_type="minicon", with_l2=False,
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with_test_gen=False, **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, ramcon_type=ramcon_type,
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with_l2=with_l2,
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(),
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**kwargs)
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platform.add_extension(_tester_io)
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