forked from M-Labs/artiq
adapt code to MiSoC's changes
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@ -3,7 +3,7 @@ from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib import gpio
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from misoclib.cpu.peripherals import gpio
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from targets.kc705 import BaseSoC
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from artiqlib import rtio, ad9858
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@ -3,7 +3,7 @@ from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib import gpio
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from misoclib.cpu.peripherals import gpio
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from targets.ppro import BaseSoC
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from artiqlib import rtio, ad9858
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@ -96,6 +96,7 @@ class ARTIQMiniSoC(BaseSoC):
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with_test_gen=False, **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, ramcon_type=ramcon_type,
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with_l2=with_l2,
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**kwargs)
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platform.add_extension(_tester_io)
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