forked from M-Labs/artiq
kc705: 16 TTLs
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@ -90,7 +90,7 @@ class _ARTIQSoCPeripherals(BaseSoC):
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
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rtio_outs = [platform.request("ttl", i) for i in range(16)] + [fud]
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self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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