forked from M-Labs/artiq
rtio: make 63-bit timestamp counter the default [soc]
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@ -294,7 +294,7 @@ class _RTIOBankI(Module):
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, clk_freq, counter_width=32,
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def __init__(self, phy, clk_freq, counter_width=63,
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ofifo_depth=64, ififo_depth=64,
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guard_io_cycles=20):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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@ -119,6 +119,7 @@ class ARTIQMiniSoC(BaseSoC):
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output_only_pads=set(rtio_outs))
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self.submodules.rtio = rtio.RTIO(self.rtiophy,
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clk_freq=125000000,
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counter_width=32,
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ififo_depth=512)
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rtio_csrs = self.rtio.get_csrs()
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