forked from M-Labs/artiq
soc: add_cpu_csr_region -> add_csr_region
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@ -103,7 +103,7 @@ class ARTIQSoC(BaseSoC):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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@ -122,7 +122,7 @@ class ARTIQMiniSoC(BaseSoC):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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if with_test_gen:
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self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
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