targets/ppro: disable L2

2015-02-27 18:02:21 -07:00 · 2015-02-27 18:02:21 -07:00 · 7028d85255
parent 0127de9bb5
commit 7028d85255
1 changed files with 2 additions and 1 deletions
--- a/soc/targets/artiq_ppro.py
+++ b/soc/targets/artiq_ppro.py
@ -92,7 +92,8 @@ class ARTIQMiniSoC(BaseSoC):
    }
    csr_map.update(BaseSoC.csr_map)

-    def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
+    def __init__(self, platform, cpu_type="or1k",
+                 ramcon_type="minicon", with_l2=False,
                 with_test_gen=False, **kwargs):
        BaseSoC.__init__(self, platform,
                         cpu_type=cpu_type, ramcon_type=ramcon_type,