forked from M-Labs/artiq
pipistrello: use mem_decoder
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@ -4,6 +4,7 @@ from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from targets.pipistrello import BaseSoC
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from artiq.gateware import rtio, ad9858
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@ -124,12 +125,12 @@ class ARTIQMidiSoC(BaseSoC):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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self.comb += dds_pads.fud_n.eq(~fud)
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