Sebastien Bourdeauducq
117b361a06
Merge branch 'master' of github.com:m-labs/artiq
2015-07-27 11:42:29 +08:00
Sebastien Bourdeauducq
3573fd02a6
targets/kc705: add TIG constraints for ISE
2015-07-27 10:58:19 +08:00
Sebastien Bourdeauducq
fe6a5c42df
rtio: remove unused clk_freq argument
2015-07-27 10:57:15 +08:00
Robert Jördens
d65d303ac6
pipistrello: remove unused constraint kwarg
2015-07-26 17:39:07 -06:00
Sebastien Bourdeauducq
34aacd3c5f
complete AD9914 support (no programmable modulus, untested)
2015-07-08 17:22:43 +02:00
Robert Jördens
959ba99f1c
pipistrello: try simpler constraints
2015-07-04 21:08:28 -06:00
Sebastien Bourdeauducq
753d61b38f
complete support for TTL clock generator
2015-07-04 18:36:01 +02:00
Sebastien Bourdeauducq
0a9f9093f7
kc705: fix ttl15
2015-07-02 20:02:05 +02:00
Sebastien Bourdeauducq
2881d5f00a
gateware: add RTIO clock generator
2015-07-02 18:20:26 +02:00
Robert Jördens
3ee2bd5fa8
pipistrello: set CLKFX_MD_MAX from MD ratio
2015-06-29 12:59:59 -06:00
Robert Jördens
d1c4cf0b78
pipistrello: update rtio channel doc
2015-06-29 12:21:54 -06:00
Robert Jördens
f0ac8cb354
pipistrello: add user_led:2 for debugging w/o adapter
2015-06-29 11:30:37 -06:00
Robert Jördens
d39382eca0
pipistrello: ext_led fifo depth 4
2015-06-28 22:06:33 -06:00
Robert Jördens
165ef20ffa
pipistrello: drop rtio fifos for invisible leds
...
the main board leds are all under the adapter board
also tweak fifo depths a bit in a feeble attempt to circumvent a ISE hang (par
phase 4)
2015-06-28 21:24:57 -06:00
Robert Jördens
e2cb0e107f
pipistrello: really do not request xtrig
2015-06-28 21:11:41 -06:00
Robert Jördens
23eee94458
pipistrello: add notes to nist_qc1 about dds_clock
...
* remove xtrig from the target as it is not usually connected (used for
dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock.
* this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt
inputs followed by 16 ttl outputs followed by leds)
2015-06-28 20:56:12 -06:00
Sebastien Bourdeauducq
944bfafefa
soc: support QC2 and AD9914 (untested)
2015-06-28 21:37:27 +02:00
Sebastien Bourdeauducq
a7bbcdc1ad
targets/pipistrello: mon -> moninj
2015-06-27 21:15:17 +02:00
Robert Jördens
5b3eac1d96
pipistrello: tweak fifo depths a bit
...
ise being dull again, inferring all but one 64x64 fifo as bram...
minimum bram depth is 256 anyway
2015-06-22 23:25:07 -06:00
Robert Jördens
cd249b2f66
pipistrello: run at 83+1/3 MHz, cleanup CRG
2015-06-22 19:03:00 -06:00
Sebastien Bourdeauducq
9f3f9255a2
soc: increase DDS output FIFO sizes
2015-06-21 08:40:10 -06:00
Sebastien Bourdeauducq
5a9bdb2e33
DDS monitoring
2015-06-19 15:30:17 -06:00
Sebastien Bourdeauducq
03fe71228b
dds: phase computation fixes
2015-06-19 11:01:43 -06:00
Sébastien Bourdeauducq
3636025e69
pipistrello: smaller L2 cache
2015-06-18 09:49:52 -06:00
Florent Kermarrec
38a0f63bd2
gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache
2015-06-18 12:18:03 +02:00
Sebastien Bourdeauducq
b2af0f6cc3
soc,runtime: support TTL override
2015-06-09 19:51:02 +08:00
Sebastien Bourdeauducq
a2ae5e4706
runtime: report TTL status over UDP
2015-06-03 18:26:19 +08:00
Sebastien Bourdeauducq
b81151eb42
soc: rtio monitor
2015-06-02 17:41:40 +08:00
Sebastien Bourdeauducq
a36c51eb83
DDS over RTIO (batch mode not supported yet)
2015-05-08 14:44:39 +08:00
Sebastien Bourdeauducq
a91bb48ced
gateware: adapt to misoc changes
2015-05-06 18:02:15 +08:00
Sebastien Bourdeauducq
a61d701d47
rtio: decouple PHY reset from logic reset
2015-05-02 11:47:11 +08:00
Sebastien Bourdeauducq
62669f9ff2
soc: factor timer, kernel CPU and mailbox
2015-05-01 18:51:24 +08:00
Sebastien Bourdeauducq
967145f2dc
watchdog support on core device (broken by bug similar to issue #19 )
2015-04-29 12:58:37 +08:00
Sebastien Bourdeauducq
86c012924e
targets: rename AMP->Top, merge peripherals
2015-04-28 00:18:54 +08:00
Sebastien Bourdeauducq
938e1c2842
Remove UP support.
...
The only advantage of UP is to support the Papilio Pro, but that port is also very limited in other ways and the Pipistrello provides a more reasonable platform that also supports AMP.
On the other hand, RPCs on UP are difficult to implement with the session.c protocol system (without an operating system or coroutines), along with many other minor difficulties and maintainance issues. Planned features such as watchdogs in the core device are also difficult on UP.
2015-04-27 20:43:45 +08:00
Sebastien Bourdeauducq
546996f896
coredevice,runtime: put ref_period into the ddb
2015-04-16 15:15:38 +08:00
Sebastien Bourdeauducq
61a6506484
targets/pipistrello: add mailbox memory region
2015-04-15 20:41:28 +08:00
Florent Kermarrec
fd2def4951
generate MAILBOX_BASE with SoC and use it in runtime
...
to avoid possible future mismatches between SoC/runtime, constants that can be easily generated from SoC should be defined this way.
2015-04-15 20:40:28 +08:00
Robert Jördens
f988ec318e
pipistrello: fix csrs, make AMP default
2015-04-14 21:10:07 -06:00
Robert Jördens
9e726d7dd1
ppro: ignore all async paths
2015-04-14 18:18:48 -06:00
Robert Jördens
70916aa0c5
pipistrello: tig _all_ async paths, add timing interference report
2015-04-14 18:18:48 -06:00
Robert Jördens
066adbdeac
pipistrello: timing report
2015-04-14 18:18:16 -06:00
Robert Jördens
6217cf5392
pipistrello: basesoc, cleanup
2015-04-14 18:18:16 -06:00
Sebastien Bourdeauducq
4c10182c9f
rtio: refactor, use rtlink
2015-04-14 19:44:45 +08:00
Sebastien Bourdeauducq
c0f1708c20
targets/pipstrello: fix mem_map
2015-04-14 19:34:14 +08:00
Sebastien Bourdeauducq
a50f2c20ff
targets/ppro: fix mem_map update
2015-04-11 21:59:29 +08:00
Sebastien Bourdeauducq
601f593ac4
targets/kc705: do not depend on particular Migen generated signal names
2015-04-11 21:46:57 +08:00
Florent Kermarrec
bdd02a064e
targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
2015-04-11 21:32:46 +08:00
Florent Kermarrec
24b2bd7b6f
soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
2015-04-11 21:32:11 +08:00
Sebastien Bourdeauducq
fb75bd246e
targets/kc705: make AMP the default
2015-04-11 17:16:25 +08:00