targets/pipstrello: fix mem_map

2015-04-14 19:34:14 +08:00 · 2015-04-14 19:34:14 +08:00 · c0f1708c20
parent ff9a7727d2
commit c0f1708c20
1 changed files with 1 additions and 1 deletions
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@ -55,7 +55,7 @@ class _Peripherals(BaseSoC):
        "rtio":     0x20000000, # (shadow @0xa0000000)
        "dds":      0x50000000, # (shadow @0xd0000000)
    }
-    mem_map.update(MiniSoC.mem_map)
+    mem_map.update(BaseSoC.mem_map)

    def __init__(self, platform, cpu_type="or1k", **kwargs):
        BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)