forked from M-Labs/artiq
pipistrello: add notes to nist_qc1 about dds_clock
* remove xtrig from the target as it is not usually connected (used for dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock. * this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt inputs followed by 16 ttl outputs followed by leds)
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@ -4,10 +4,22 @@ from mibuild.generic_platform import *
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papilio_adapter_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
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# to the FPGA, use the xtrig pair.
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#
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# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
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#
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# on pipistrello, C:15 is the only GCLK in proximity, used as a button
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# input, BTN2/PMT2 in papiliopro-adapter
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# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
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#
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# * disconnect C:15 from its periphery on the adapter board
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# * bridge C:15 to the xtrig output of the transciever
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# * optionally, disconnect C:12 from its periphery
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2
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("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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@ -34,7 +34,7 @@ class _RTIOCRG(Module, AutoCSR):
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i_FREEZEDCM=0,
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i_RST=ResetSignal())
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rtio_external_clk = platform.request("dds_clock")
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rtio_external_clk = platform.request("pmt", 2)
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platform.add_period_constraint(rtio_external_clk, 8.0)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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@ -95,11 +95,13 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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for i in range(2):
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phy = ttl_simple.Inout(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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ofifo_depth=4))
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phy = ttl_simple.Inout(platform.request("xtrig", 0))
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phy = ttl_simple.Inout(platform.request("xtrig"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
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ofifo_depth=4))
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for i in range(16):
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phy = ttl_simple.Output(platform.request("ttl", i))
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