forked from M-Labs/artiq
gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache
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parent
2f8a67c8b6
commit
38a0f63bd2
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@ -3,12 +3,11 @@ from migen.bank.description import *
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from migen.bus import wishbone
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from misoclib.cpu import mor1kx
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from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
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from misoclib.soc import mem_decoder
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class KernelCPU(Module):
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def __init__(self, platform, lasmim,
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def __init__(self, platform,
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exec_address=0x40400000,
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main_mem_origin=0x40000000,
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l2_size=8192):
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@ -29,16 +28,8 @@ class KernelCPU(Module):
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"sys_kernel")
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# DRAM access
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# XXX Vivado 2014.X workaround
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE()(
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WB2LASMI(l2_size//4, lasmim))
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else:
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self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
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self.add_wb_slave(mem_decoder(main_mem_origin),
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self.wishbone2lasmi.wishbone)
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self.wb_sdram = wishbone.Interface()
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self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
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def get_csrs(self):
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return [self._reset]
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@ -19,8 +19,9 @@ class AMPSoC:
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self.submodules.timer0 = timer.Timer(width=64)
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self.submodules.kernel_cpu = amp.KernelCPU(
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self.platform, self.sdram.crossbar.get_master())
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self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
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self.add_wb_sdram_if(self.kernel_cpu.wb_sdram)
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i1)
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@ -6,6 +6,7 @@ from mibuild.xilinx.vivado import XilinxVivadoToolchain
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.kc705 import MiniSoC
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from artiq.gateware.soc import AMPSoC
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@ -48,7 +49,9 @@ class NIST_QC1(MiniSoC, AMPSoC):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self, platform,
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cpu_type=cpu_type, with_timer=False, **kwargs)
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(l2_size=128*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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@ -4,6 +4,7 @@ from migen.bank import wbgen
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.pipistrello import BaseSoC
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from artiq.gateware.soc import AMPSoC
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@ -69,7 +70,9 @@ class NIST_QC1(BaseSoC, AMPSoC):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, with_timer=False, **kwargs)
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(l2_size=128*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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platform.toolchain.ise_commands += """
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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