kc705: fix ttl15

2015-07-02 20:02:05 +02:00 · 2015-07-02 20:02:05 +02:00 · 0a9f9093f7
parent 2881d5f00a
commit 0a9f9093f7
1 changed files with 1 additions and 1 deletions
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@ -129,7 +129,7 @@ class NIST_QC2(_NIST_QCx):
        for i in range(16):
            if i == 14:
                # TTL14 is for the clock generator
-                break
+                continue
            if i % 4 == 3:
                phy = ttl_simple.Inout(platform.request("ttl", i))
                self.submodules += phy