Florent Kermarrec bdd02a064e targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)		2015-04-11 21:32:46 +08:00
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artiq_kc705.py	targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)	2015-04-11 21:32:46 +08:00
artiq_pipistrello.py	soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds	2015-04-11 21:32:11 +08:00
artiq_ppro.py	soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds	2015-04-11 21:32:11 +08:00