forked from M-Labs/artiq
DDS monitoring
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03fe71228b
commit
5a9bdb2e33
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@ -51,13 +51,12 @@ class DDS(AutoDB):
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Controls one DDS channel managed directly by the core device's runtime.
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:param dds_sysclk: DDS system frequency, used for computing the frequency
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tuning words.
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:param sysclk: DDS system frequency.
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:param channel: channel number of the DDS device to control.
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"""
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class DBKeys:
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core = Device()
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dds_sysclk = Argument(1*GHz)
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sysclk = Argument()
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channel = Argument()
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def build(self):
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@ -68,14 +67,14 @@ class DDS(AutoDB):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(2**32*frequency/self.dds_sysclk)
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return round(2**32*frequency/self.sysclk)
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@portable
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw*self.dds_sysclk/2**32
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return ftw*self.sysclk/2**32
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@kernel
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def init(self):
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@ -11,6 +11,7 @@ class Monitor(Module, AutoCSR):
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max_probe_len = max(flen(p) for cp in chan_probes for p in cp)
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self.chan_sel = CSRStorage(bits_for(len(chan_probes)-1))
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self.probe_sel = CSRStorage(bits_for(max_chan_probes-1))
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self.value_update = CSR()
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self.value = CSRStatus(max_probe_len)
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# # #
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@ -25,8 +26,9 @@ class Monitor(Module, AutoCSR):
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cp_sys.append(vs.o)
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cp_sys += [0]*(max_chan_probes-len(cp))
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chan_probes_sys.append(Array(cp_sys)[self.probe_sel.storage])
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self.comb += self.value.status.eq(
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Array(chan_probes_sys)[self.chan_sel.storage])
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self.sync += If(self.value_update.re,
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self.value.status.eq(
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Array(chan_probes_sys)[self.chan_sel.storage]))
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class Injector(Module, AutoCSR):
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@ -0,0 +1,36 @@
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from migen.fhdl.std import *
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from artiq.gateware import ad9858 as ad9858_ll
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class AD9858(Module):
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def __init__(self, pads, nchannels=8, **kwargs):
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self.submodules._ll = RenameClockDomains(
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ad9858_ll.AD9858(pads, **kwargs), "rio")
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self.submodules._rt2wb = RT2WB(7, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = [Signal(32) for i in range(nchannels)]
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# # #
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# keep track of the currently selected channel
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current_channel = Signal(max=nchannels)
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 65),
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current_channel.eq(self.rtlink.o.data))
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# keep track of frequency tuning words, before they are FUDed
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ftws = [Signal(32) for i in range(nchannels)]
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for i in range(4):
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for c, ftw in enumerate(ftws):
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self.sync.rio += \
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If(self.rtlink.o.stb & \
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(self.rtlink.o.address == 0x0a+i) & \
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(current_channel == c),
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ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
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)
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# FTW to probe on FUD
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for c, (probe, ftw) in enumerate(zip(self.probes, ftw)):
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fud = self.rtlink.o.stb & (self.rtlink.o.address == 64)
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self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
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@ -9,6 +9,7 @@ from pyqtgraph import dockarea
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from artiq.tools import TaskObject
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from artiq.protocols.sync_struct import Subscriber
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from artiq.language.units import strip_unit
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logger = logging.getLogger(__name__)
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@ -112,9 +113,10 @@ class _TTLWidget(QtGui.QFrame):
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class _DDSWidget(QtGui.QFrame):
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def __init__(self, send_to_device, channel, name):
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def __init__(self, send_to_device, channel, sysclk, name):
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self.send_to_device = send_to_device
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self.channel = channel
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self.sysclk = sysclk
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self.name = name
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QtGui.QFrame.__init__(self)
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@ -128,48 +130,16 @@ class _DDSWidget(QtGui.QFrame):
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label.setAlignment(QtCore.Qt.AlignCenter)
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grid.addWidget(label, 1, 1)
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self._override = QtGui.QLabel()
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self._override.setAlignment(QtCore.Qt.AlignCenter)
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grid.addWidget(self._override, 2, 1)
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self._value = QtGui.QLabel()
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self._value.setAlignment(QtCore.Qt.AlignCenter)
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grid.addWidget(self._value, 3, 1, 6, 1)
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grid.addWidget(self._value, 2, 1, 6, 1)
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self._value.setContextMenuPolicy(QtCore.Qt.ActionsContextMenu)
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self._override_action = QtGui.QAction("Override", self._value)
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self._override_action.setCheckable(True)
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self._value.addAction(self._override_action)
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self._override_action.triggered.connect(self._override_clicked)
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self.set_value(0)
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self.set_value(0.0, False)
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def _override_clicked(self):
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override_en = self._override_action.isChecked()
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if override_en:
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frequency, ok = QtGui.QInputDialog.getDouble(
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None, "DDS override",
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"Frequency in MHz for {}:".format(self.name),
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value=self._frequency, min=0, decimals=3)
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self._override_action.setChecked(ok)
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if ok:
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print("override set to", frequency)
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else:
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print("override disabled")
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def set_value(self, frequency, override):
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self._frequency = frequency
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self._override_action.setChecked(override)
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value_s = "{:.3f} MHz".format(frequency)
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if override:
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value_s = "<b>" + value_s + "</b>"
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color = " color=\"red\""
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self._override.setText("<font size=\"1\" color=\"red\">OVERRIDE</font>")
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else:
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color = ""
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self._override.setText("")
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self._value.setText("<font size=\"9\"{}>{}</font>"
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.format(color, value_s))
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def set_value(self, ftw):
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frequency = ftw*self.sysclk/2**32
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self._value.setText("<font size=\"9\">{:.3f} MHz</font>"
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.format(float(frequency)))
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class _DeviceManager:
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@ -200,8 +170,9 @@ class _DeviceManager:
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if (v["module"] == "artiq.coredevice.dds"
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and v["class"] == "DDS"):
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channel = v["arguments"]["channel"]
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sysclk = strip_unit(v["arguments"]["sysclk"], "Hz")
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self.dds_widgets[channel] = _DDSWidget(
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self.send_to_device, channel, k)
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self.send_to_device, channel, sysclk, k)
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self.dds_cb()
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except KeyError:
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pass
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@ -277,11 +248,25 @@ class MonInj(TaskObject):
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self.transport = transport
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def datagram_received(self, data, addr):
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ttl_levels, ttl_oes, ttl_overrides = struct.unpack(">QQQ", data)
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for channel, w in self.dm.ttl_widgets.items():
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w.set_value(ttl_levels & (1 << channel),
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ttl_oes & (1 << channel),
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ttl_overrides & (1 << channel))
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try:
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ttl_levels, ttl_oes, ttl_overrides = \
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struct.unpack(">QQQ", data[:8*3])
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for channel, w in self.dm.ttl_widgets.items():
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w.set_value(ttl_levels & (1 << channel),
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ttl_oes & (1 << channel),
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ttl_overrides & (1 << channel))
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dds_data = data[8*3:]
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ndds = len(dds_data)//4
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ftws = struct.unpack(">" + "I"*ndds, dds_data)
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for channel, w in self.dm.dds_widgets.items():
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try:
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ftw = ftws[channel]
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except KeyError:
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pass
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else:
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w.set_value(ftw)
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except:
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logger.warning("failed to process datagram", exc_info=True)
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def error_received(self, exc):
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logger.warning("datagram endpoint error")
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@ -60,19 +60,22 @@
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDS",
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"arguments": {"channel": 0}
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"arguments": {"sysclk": Quantity(Fraction(1000000000, 1), "Hz"),
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"channel": 0}
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},
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"dds1": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDS",
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"arguments": {"channel": 1}
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"arguments": {"sysclk": Quantity(Fraction(1000000000, 1), "Hz"),
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"channel": 1}
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},
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"dds2": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDS",
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"arguments": {"channel": 2}
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"arguments": {"sysclk": Quantity(Fraction(1000000000, 1), "Hz"),
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"channel": 2}
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},
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"qc_q1_0": {
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@ -61,7 +61,7 @@ static void dds_set_one(long long int now, long long int ref_time, int channel,
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DDS_WRITE(DDS_FTW3, (ftw >> 24) & 0xff);
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/* We need the RTIO fine timestamp clock to be phase-locked
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* to DDS SYNCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
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* to DDS SYSCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
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*/
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if(phase_mode == PHASE_MODE_CONTINUOUS) {
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/* Do not clear phase accumulator on FUD */
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@ -4,9 +4,6 @@
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#include <hw/common.h>
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#include <generated/mem.h>
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/* Number of DDS channels to initialize */
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#define DDS_CHANNEL_COUNT 8
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/* Maximum number of commands in a batch */
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#define DDS_MAX_BATCH 16
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@ -39,6 +39,7 @@ struct monitor_reply {
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long long int ttl_levels;
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long long int ttl_oes;
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long long int ttl_overrides;
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unsigned int dds_ftws[DDS_CHANNEL_COUNT];
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};
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static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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@ -53,9 +54,11 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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for(i=0;i<RTIO_TTL_COUNT;i++) {
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rtio_moninj_mon_chan_sel_write(i);
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rtio_moninj_mon_probe_sel_write(0);
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rtio_moninj_mon_value_update_write(1);
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if(rtio_moninj_mon_value_read())
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reply.ttl_levels |= 1LL << i;
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rtio_moninj_mon_probe_sel_write(1);
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rtio_moninj_mon_value_update_write(1);
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if(rtio_moninj_mon_value_read())
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reply.ttl_oes |= 1LL << i;
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rtio_moninj_inj_chan_sel_write(i);
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@ -64,6 +67,13 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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reply.ttl_overrides |= 1LL << i;
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}
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rtio_moninj_mon_chan_sel_write(RTIO_DDS_CHANNEL);
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for(i=0;i<DDS_CHANNEL_COUNT;i++) {
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rtio_moninj_mon_probe_sel_write(i);
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rtio_moninj_mon_value_update_write(1);
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reply.dds_ftws[i] = rtio_moninj_mon_value_read();
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}
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reply_p = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct monitor_reply), PBUF_RAM);
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if(!reply_p) {
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log("Failed to allocate pbuf for monitor reply");
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@ -10,9 +10,8 @@ from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.kc705 import MiniSoC
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, ad9858, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple, dds
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class _RTIOCRG(Module, AutoCSR):
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@ -81,10 +80,8 @@ class NIST_QC1(MiniSoC, AMPSoC):
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.submodules.dds = RenameClockDomains(
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ad9858.AD9858(platform.request("dds")),
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"rio")
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phy = RT2WB(7, self.dds.bus)
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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@ -8,9 +8,8 @@ from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.pipistrello import BaseSoC
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, ad9858, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple, dds
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class _RTIOCRG(Module, AutoCSR):
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@ -116,10 +115,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.submodules.dds = RenameClockDomains(
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ad9858.AD9858(platform.request("dds")),
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"rio")
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phy = RT2WB(7, self.dds.bus)
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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