artiq/soc/targets
2015-06-18 12:18:03 +02:00
..
artiq_kc705.py gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache 2015-06-18 12:18:03 +02:00
artiq_pipistrello.py gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache 2015-06-18 12:18:03 +02:00