forked from M-Labs/artiq
soc: increase DDS output FIFO sizes
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@ -83,7 +83,9 @@ class NIST_QC1(MiniSoC, AMPSoC):
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)
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@ -118,7 +118,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform)
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