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pipistrello: drop rtio fifos for invisible leds

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the main board leds are all under the adapter board

also tweak fifo depths a bit in a feeble attempt to circumvent a ISE hang (par
phase 4)
This commit is contained in:
Robert Jördens 2015-06-28 21:24:57 -06:00
parent e2cb0e107f
commit 165ef20ffa
1 changed files with 1 additions and 5 deletions
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6
soc/targets/artiq_pipistrello.py
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@ -105,12 +105,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
for i in range(2, 5):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))