rtio: decouple PHY reset from logic reset

artiq/gateware/rtio/core.py

@@ -257,6 +257,7 @@ class _KernelCSRs(AutoCSR):
     def __init__(self, chan_sel_width,
                  data_width, address_width, full_ts_width):
         self.reset = CSRStorage(reset=1)
+        self.reset_phy = CSRStorage(reset=1)
         self.chan_sel = CSRStorage(chan_sel_width)
 
         if data_width:
@@ -296,10 +297,11 @@ class RTIO(Module):
                                  full_ts_width)
 
         # Clocking/Reset
-        # Create rsys and rio domains based on sys and rio
+        # Create rsys, rio and rio_phy domains based on sys and rtio
         # with reset controlled by CSR.
         self.clock_domains.cd_rsys = ClockDomain()
         self.clock_domains.cd_rio = ClockDomain()
+        self.clock_domains.cd_rio_phy = ClockDomain()
         self.comb += [
             self.cd_rsys.clk.eq(ClockSignal()),
             self.cd_rsys.rst.eq(self.kcsrs.reset.storage)
@@ -307,6 +309,9 @@ class RTIO(Module):
         self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
         self.specials += AsyncResetSynchronizer(self.cd_rio,
                                                 self.kcsrs.reset.storage)
+        self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
+        self.specials += AsyncResetSynchronizer(self.cd_rio_phy,
+                                                self.kcsrs.reset_phy.storage)
 
         # Managers
         self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)

artiq/gateware/rtio/phy/ttl_simple.py

@@ -10,7 +10,7 @@ class Output(Module):
 
         # # #
 
-        self.sync.rio += If(self.rtlink.o.stb, pad.eq(self.rtlink.o.data))
+        self.sync.rio_phy += If(self.rtlink.o.stb, pad.eq(self.rtlink.o.data))
 
 
 class Inout(Module):
@@ -25,7 +25,7 @@ class Inout(Module):
         self.specials += ts.get_tristate(pad)
         sensitivity = Signal(2)
 
-        self.sync.rio += If(self.rtlink.o.stb,
+        self.sync.rio_phy += If(self.rtlink.o.stb,
             Case(self.rtlink.o.address, {
                 0: ts.o.eq(self.rtlink.o.data[0]),
                 1: ts.oe.eq(self.rtlink.o.data[0]),
@@ -35,8 +35,8 @@ class Inout(Module):
         
         i = Signal()
         i_d = Signal()
-        self.specials += MultiReg(ts.i, i, "rio")
-        self.sync.rio += i_d.eq(i)
+        self.specials += MultiReg(ts.i, i, "rio_phy")
+        self.sync.rio_phy += i_d.eq(i)
         self.comb += [
             self.rtlink.i.stb.eq(
                 (sensitivity[0] & ( i & ~i_d)) |

artiq/gateware/rtio/phy/wishbone.py

@@ -18,7 +18,7 @@ class RT2WB(Module):
         # # #
 
         active = Signal()
-        self.sync.rio += [
+        self.sync.rio_phy += [
             If(self.rtlink.o.stb,
                 active.eq(1),
                 wb.adr.eq(self.rtlink.o.address[:address_width]),

soc/runtime/rtio.c

@@ -16,6 +16,7 @@ void rtio_init(void)
     previous_fud_end_time = 0;
     rtio_reset_write(1);
     rtio_reset_write(0);
+    rtio_reset_phy_write(0);
 }
 
 static void write_and_process_status(long long int timestamp, int channel)

soc/targets/artiq_kc705.py

@@ -17,7 +17,7 @@ from artiq.gateware.rtio.phy import ttl_simple
 class _RTIOCRG(Module, AutoCSR):
     def __init__(self, platform, rtio_internal_clk):
         self._clock_sel = CSRStorage()
-        self.clock_domains.cd_rtio = ClockDomain()
+        self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
 
         rtio_external_clk = Signal()
         user_sma_clock = platform.request("user_sma_clock")

soc/targets/artiq_pipistrello.py

@@ -14,7 +14,7 @@ from artiq.gateware.rtio.phy import ttl_simple
 class _RTIOCRG(Module, AutoCSR):
     def __init__(self, platform):
         self._clock_sel = CSRStorage()
-        self.clock_domains.cd_rtio = ClockDomain()
+        self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
 
         # 75MHz -> 125MHz
         rtio_internal_clk = Signal()