forked from M-Labs/artiq
runtime: report TTL status over UDP
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@ -1,2 +1,2 @@
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from artiq.gateware.rtio.core import Channel, RTIO
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from artiq.gateware.rtio.monitor import Monitor
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from artiq.gateware.rtio.moninj import Monitor
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@ -2,6 +2,7 @@ from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.cdc import BusSynchronizer
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class Monitor(Module, AutoCSR):
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def __init__(self, channels):
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chan_probes = [c.probes for c in channels]
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@ -1,6 +1,6 @@
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include $(MSCDIR)/software/common.mak
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OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o main.o
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OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o moninj.o main.o
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OBJECTS_KSUPPORT := ksupport.o exception_jmp.o exceptions.o mailbox.o bridge.o rtio.o ttl.o dds.o
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CFLAGS += -Ilwip/src/include -Iliblwip
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@ -66,7 +66,7 @@ a lot of data that needs to be copied, this should be set high. */
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#define MEMP_NUM_PBUF 64
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/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
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per active UDP "connection". */
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#define MEMP_NUM_UDP_PCB 1
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#define MEMP_NUM_UDP_PCB 2
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/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
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connections. */
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#define MEMP_NUM_TCP_PCB 8
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@ -159,7 +159,7 @@ a lot of data that needs to be copied, this should be set high. */
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#define DHCP_DOES_ARP_CHECK 0
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/* ---------- UDP options ---------- */
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#define LWIP_UDP 0
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#define LWIP_UDP 1
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#define UDP_TTL 255
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@ -28,6 +28,7 @@
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#include "test_mode.h"
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#include "kserver.h"
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#include "session.h"
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#include "moninj.h"
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static void common_init(void)
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{
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@ -139,6 +140,7 @@ static void regular_main(void)
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puts("Accepting sessions on Ethernet.");
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network_init();
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kserver_init();
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moninj_init();
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session_end();
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while(1) {
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@ -0,0 +1,83 @@
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#include <generated/csr.h>
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#ifdef CSR_ETHMAC_BASE
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#include <netif/etharp.h>
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#include <lwip/init.h>
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#include <lwip/memp.h>
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#include <lwip/ip4_addr.h>
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#include <lwip/ip4.h>
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#include <lwip/netif.h>
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#include <lwip/sys.h>
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#include <lwip/udp.h>
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#include <lwip/timers.h>
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#include "log.h"
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#include "moninj.h"
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enum {
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MONINJ_REQ_MONITOR = 1
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};
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static struct udp_pcb *listen_pcb;
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struct monitor_reply {
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long long int ttl_levels;
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long long int ttl_oes;
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};
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static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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{
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struct monitor_reply reply;
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int i;
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struct pbuf *reply_p;
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reply.ttl_levels = 0;
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reply.ttl_oes = 0;
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for(i=0;i<RTIO_TTL_COUNT;i++) {
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rtio_mon_chan_sel_write(i);
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rtio_mon_probe_sel_write(0);
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if(rtio_mon_probe_value_read())
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reply.ttl_levels |= 1LL << i;
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rtio_mon_probe_sel_write(1);
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if(rtio_mon_probe_value_read())
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reply.ttl_oes |= 1LL << i;
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}
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reply_p = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct monitor_reply), PBUF_RAM);
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if(!reply_p) {
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log("Failed to allocate pbuf for monitor reply");
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return;
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}
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memcpy(reply_p->payload, &reply, sizeof(struct monitor_reply));
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udp_sendto(listen_pcb, reply_p, addr, port);
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pbuf_free(reply_p);
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}
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static void moninj_recv(void *arg, struct udp_pcb *upcb, struct pbuf *req,
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const ip_addr_t *addr, u16_t port)
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{
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if(req->len >= 1) {
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switch(*(char *)req->payload) {
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case MONINJ_REQ_MONITOR:
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moninj_monitor(addr, port);
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break;
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default:
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break;
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}
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}
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pbuf_free(req); /* beware: addr may point into the req pbuf */
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}
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void moninj_init(void)
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{
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listen_pcb = udp_new();
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if(!listen_pcb) {
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log("Failed to create UDP listening PCB");
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return;
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}
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udp_bind(listen_pcb, IP_ADDR_ANY, 3250);
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udp_recv(listen_pcb, moninj_recv, NULL);
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}
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#endif /* CSR_ETHMAC_BASE */
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@ -0,0 +1,6 @@
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#ifndef __MONINJ_H
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#define __MONINJ_H
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void moninj_init(void);
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#endif /* __MONINJ_H */
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@ -76,6 +76,7 @@ class NIST_QC1(MiniSoC, AMPSoC):
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.submodules.dds = RenameClockDomains(
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@ -111,6 +111,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.submodules.dds = RenameClockDomains(
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