forked from M-Labs/artiq
soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
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parent
fb75bd246e
commit
24b2bd7b6f
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@ -2,12 +2,13 @@
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#define __DDS_H
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#include <hw/common.h>
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#include <generated/mem.h>
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#define DDS_READ(addr) \
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MMPTR(0xb0000000 + (addr)*4)
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MMPTR(DDS_BASE + (addr)*4)
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#define DDS_WRITE(addr, data) \
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MMPTR(0xb0000000 + (addr)*4) = data
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MMPTR(DDS_BASE + (addr)*4) = data
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#define DDS_FTW0 0x0a
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#define DDS_FTW1 0x0b
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@ -34,6 +34,11 @@ class _Peripherals(MiniSoC):
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"rtiocrg": 13
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}
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csr_map.update(MiniSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self, platform,
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@ -74,17 +79,21 @@ class UP(_Peripherals):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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mem_map = {
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(_Peripherals.mem_map)
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def __init__(self, platform, *args, **kwargs):
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_Peripherals.__init__(self, platform, *args, **kwargs)
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@ -92,15 +101,15 @@ class AMP(_Peripherals):
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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default_subtarget = AMP
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@ -51,6 +51,11 @@ class _Peripherals(BaseSoC):
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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@ -93,17 +98,21 @@ class UP(_Peripherals):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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mem_map = {
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(_Peripherals.mem_map)
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def __init__(self, platform, *args, **kwargs):
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_Peripherals.__init__(self, platform, **kwargs)
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@ -111,15 +120,16 @@ class AMP(_Peripherals):
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.kernel_cpu.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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default_subtarget = UP
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@ -4,6 +4,7 @@ from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.ppro import BaseSoC
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@ -59,6 +60,11 @@ class UP(BaseSoC):
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"rtiocrg": 13
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k",
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with_test_gen=False, **kwargs):
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@ -93,15 +99,16 @@ class UP(BaseSoC):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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if with_test_gen:
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self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
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self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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self.comb += dds_pads.fud_n.eq(~fud)
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