forked from M-Labs/artiq
pipistrello: really do not request xtrig
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@ -98,11 +98,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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ofifo_depth=4))
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phy = ttl_simple.Inout(platform.request("xtrig"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
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ofifo_depth=4))
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for i in range(16):
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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