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Merge branch 'master' of github.com:m-labs/artiq

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This commit is contained in:
Sebastien Bourdeauducq 2015-07-27 11:42:29 +08:00
commit 117b361a06
4 changed files with 36 additions and 11 deletions
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21
.travis/get-toolchain.sh
View File

@ -1,8 +1,7 @@
#!/bin/sh
packages="https://people.phys.ethz.ch/~robertjo/artiq-dev/or1k-gcc_20141105-1_amd64.deb
https://people.phys.ethz.ch/~robertjo/artiq-dev/or1k-binutils_20141105-1_amd64.deb
http://us.archive.ubuntu.com/ubuntu/pool/universe/i/iverilog/iverilog_0.9.7-1_amd64.deb"
packages="http://us.archive.ubuntu.com/ubuntu/pool/universe/i/iverilog/iverilog_0.9.7-1_amd64.deb"
archives="http://fehu.whitequark.org/files/binutils-or1k.tbz2 http://fehu.whitequark.org/files/llvm-or1k.tbz2"
mkdir -p packages
@ -13,12 +12,18 @@ do
dpkg -x $pkg_name packages
done
export PATH=$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
for a in $archives
do
wget $a
(cd packages && tar xf ../$(basename $a))
done
export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
export LD_LIBRARY_PATH=$PWD/packages/usr/lib/x86_64-linux-gnu:$PWD/packages/usr/local/x86_64-unknown-linux-gnu/or1k-elf/lib:$LD_LIBRARY_PATH
echo -e "export LD_LIBRARY_PATH=$LD_LIBRARY_PATH" >> $HOME/.mlabs/build_settings.sh
echo "export LD_LIBRARY_PATH=$LD_LIBRARY_PATH" >> $HOME/.mlabs/build_settings.sh
echo "export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PATH" >> $HOME/.mlabs/build_settings.sh
or1k-elf-as --version
or1k-elf-gcc --version
or1k-linux-as --version
llc --version
clang --version
llvm-as --version || true

12
soc/runtime/ksupport.ld
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@ -24,6 +24,17 @@ SECTIONS
_etext = .;
} > ksupport
.got :
{
_GLOBAL_OFFSET_TABLE_ = .;
*(.got)
} > ksupport
.got.plt :
{
*(.got.plt)
} > ksupport
.rodata :
{
. = ALIGN(4);
@ -39,7 +50,6 @@ SECTIONS
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ksupport

12
soc/runtime/linker.ld
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@ -26,6 +26,17 @@ SECTIONS
_etext = .;
} > runtime
.got :
{
_GLOBAL_OFFSET_TABLE_ = .;
*(.got)
} > runtime
.got.plt :
{
*(.got.plt)
} > runtime
.rodata :
{
. = ALIGN(4);
@ -41,7 +52,6 @@ SECTIONS
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > runtime

2
soc/targets/artiq_pipistrello.py
View File

@ -50,7 +50,7 @@ NET "{int_clk}" TNM_NET = "GRPint_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
""", int_clk=rtio_internal_clk)
class NIST_QC1(BaseSoC, AMPSoC):