forked from M-Labs/artiq
complete support for TTL clock generator
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a615a3830a
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753d61b38f
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@ -21,6 +21,7 @@ _syscalls = {
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"ttl_set_oe": "Iib:n",
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"ttl_set_sensitivity": "Iii:n",
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"ttl_get": "iI:I",
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"ttl_clock_set": "Iii:n",
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"dds_init": "Ii:n",
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"dds_batch_enter": "I:n",
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"dds_batch_exit": "n:n",
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@ -26,7 +26,8 @@ class TTLOut(AutoDB):
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@kernel
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def sync(self):
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"""Busy-waits until all programmed level switches have been effected."""
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"""Busy-wait until all programmed level switches have been
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effected."""
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while syscall("rtio_get_counter") < self.o_previous_timestamp:
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pass
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@ -37,12 +38,12 @@ class TTLOut(AutoDB):
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@kernel
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def off(self):
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"""Sets the output to a logic low state."""
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"""Set the output to a logic low state."""
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self.set_o(False)
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@kernel
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def pulse_mu(self, duration):
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"""Pulses the output high for the specified duration
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"""Pulse the output high for the specified duration
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(in machine units)."""
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self.on()
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delay_mu(duration)
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@ -50,7 +51,7 @@ class TTLOut(AutoDB):
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@kernel
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def pulse(self, duration):
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"""Pulses the output high for the specified duration
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"""Pulse the output high for the specified duration
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(in seconds)."""
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self.on()
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delay(duration)
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@ -103,18 +104,19 @@ class TTLInOut(AutoDB):
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@kernel
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def sync(self):
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"""Busy-waits until all programmed level switches have been effected."""
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"""Busy-wait until all programmed level switches have been
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effected."""
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while syscall("rtio_get_counter") < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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"""Sets the output to a logic high state."""
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"""Set the output to a logic high state."""
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self.set_o(True)
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@kernel
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def off(self):
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"""Sets the output to a logic low state."""
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"""Set the output to a logic low state."""
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self.set_o(False)
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@kernel
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@ -204,3 +206,69 @@ class TTLInOut(AutoDB):
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If the gate is permanently closed, returns a negative value.
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"""
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return syscall("ttl_get", self.channel, self.i_previous_timestamp)
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class TTLClockGen(AutoDB):
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"""RTIO TTL clock generator driver.
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This should be used with TTL channels that have a clock generator
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built into the gateware (not compatible with regular TTL channels).
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:param core: core device
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:param channel: channel number
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"""
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class DBKeys:
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core = Device()
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channel = Argument()
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def build(self):
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# in RTIO cycles
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self.previous_timestamp = int64(0)
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@portable
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(2**24*frequency*self.core.ref_period)
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@portable
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw/self.core.ref_period/2**24
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@kernel
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def set_mu(self, frequency):
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"""Set the frequency of the clock, in machine units.
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This also sets the phase, as the time of the first generated rising
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edge corresponds to the time of the call.
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The clock generator contains a 24-bit phase accumulator operating on
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the RTIO clock. At each RTIO clock tick, the frequency tuning word is
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added to the phase accumulator. The most significant bit of the phase
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accumulator is connected to the TTL line. Setting the frequency tuning
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word has the additional effect of setting the phase accumulator to
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0x800000.
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"""
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syscall("ttl_clock_set", now_mu(), self.channel, frequency)
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self.previous_timestamp = now_mu()
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@kernel
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def set(self, frequency):
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"""Like ``set_mu``, but using Hz."""
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self.set_mu(self.frequency_to_ftw(frequency))
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@kernel
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def stop(self):
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"""Stop the toggling of the clock and set the output level to 0."""
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self.set_mu(0)
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@kernel
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def sync(self):
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"""Busy-wait until all programmed frequency switches and stops have
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been effected."""
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while syscall("rtio_get_counter") < self.o_previous_timestamp:
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pass
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@ -78,7 +78,7 @@ class Inout(Module):
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class ClockGen(Module):
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def __init__(self, pad, ftw_width=16):
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def __init__(self, pad, ftw_width=24):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(ftw_width, suppress_nop=False))
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@ -89,7 +89,14 @@ class ClockGen(Module):
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self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
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self.sync.rio_phy += [
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acc.eq(acc + ftw),
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# known phase on write: at rising edge
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If(self.rtlink.o.stb, acc.eq(2**(ftw_width - 1))),
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If(self.rtlink.o.stb,
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If(self.rtlink.o.data != 0,
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# known phase on frequency write: at rising edge
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acc.eq(2**(ftw_width - 1))
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).Else(
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# set output to 0 on stop
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acc.eq(0)
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)
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),
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pad.eq(acc[-1])
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]
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@ -46,6 +46,26 @@ class Loopback(Experiment, AutoDB):
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self.rtt = mu_to_seconds(self.loop_in.timestamp() - t0)
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class ClockGeneratorLoopback(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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loop_clock_in = Device()
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loop_clock_out = Device()
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count = Result()
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@kernel
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def run(self):
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self.loop_clock_in.input()
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self.loop_clock_out.stop()
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delay(1*us)
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with parallel:
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self.loop_clock_in.gate_rising(10*us)
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with sequential:
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delay(200*ns)
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self.loop_clock_out.set(1*MHz)
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self.count = self.loop_clock_in.count()
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class PulseRate(Experiment, AutoDB):
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class DBKeys:
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core = Device()
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@ -81,6 +101,10 @@ class CoredeviceTest(ExperimentCase):
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self.assertGreater(rtt, 0*ns)
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self.assertLess(rtt, 50*ns)
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def test_clock_generator_loopback(self):
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count = self.execute(ClockGeneratorLoopback)["count"]
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self.assertEqual(count, 10)
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def test_pulse_rate(self):
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rate = self.execute(PulseRate)["pulse_rate"]
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print(rate)
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@ -21,6 +21,7 @@ services = [
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("ttl_set_oe", "ttl_set_oe"),
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("ttl_set_sensitivity", "ttl_set_sensitivity"),
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("ttl_get", "ttl_get"),
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("ttl_clock_set", "ttl_clock_set"),
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("dds_init", "dds_init"),
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("dds_batch_enter", "dds_batch_enter"),
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@ -51,7 +51,7 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
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reply.ttl_levels = 0;
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reply.ttl_oes = 0;
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reply.ttl_overrides = 0;
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for(i=0;i<RTIO_TTL_COUNT;i++) {
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for(i=0;i<RTIO_REGULAR_TTL_COUNT;i++) {
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rtio_moninj_mon_chan_sel_write(i);
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rtio_moninj_mon_probe_sel_write(0);
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rtio_moninj_mon_value_update_write(1);
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@ -56,3 +56,11 @@ long long int ttl_get(int channel, long long int time_limit)
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rtio_i_re_write(1);
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return r;
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}
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void ttl_clock_set(long long int timestamp, int channel, int ftw)
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{
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rtio_chan_sel_write(channel);
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rtio_o_timestamp_write(timestamp);
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rtio_o_data_write(ftw);
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rtio_write_and_process_status(timestamp, channel);
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}
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@ -5,5 +5,6 @@ void ttl_set_o(long long int timestamp, int channel, int value);
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void ttl_set_oe(long long int timestamp, int channel, int oe);
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void ttl_set_sensitivity(long long int timestamp, int channel, int sensitivity);
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long long int ttl_get(int channel, long long int time_limit);
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void ttl_clock_set(long long int timestamp, int channel, int ftw);
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#endif /* __TTL_H */
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@ -103,7 +103,7 @@ class NIST_QC1(_NIST_QCx):
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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@ -142,7 +142,7 @@ class NIST_QC2(_NIST_QCx):
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 14))
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self.submodules += phy
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@ -113,7 +113,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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