forked from M-Labs/artiq
targets/pipistrello: mon -> moninj
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@ -60,7 +60,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 13,
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"kernel_cpu": 14,
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"rtio_mon": 15
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"rtio_moninj": 15
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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@ -130,7 +130,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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clk_freq=125000000)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_mon = rtio.MonInj(rtio_channels)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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# CPU connections
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rtio_csrs = self.rtio.get_csrs()
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