forked from M-Labs/artiq
coredevice,runtime: put ref_period into the ddb
This commit is contained in:
parent
485381fdbf
commit
546996f896
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@ -108,12 +108,7 @@ class CommGeneric:
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if runtime_id != "AROR":
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raise UnsupportedDevice("Unsupported runtime ID: {}"
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.format(runtime_id))
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ref_freq_i, ref_freq_fn, ref_freq_fd = struct.unpack(
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">lBB", self._read(6))
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ref_freq = (ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))*units.Hz
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ref_period = 1/ref_freq
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logger.debug("environment ref_period: %s", ref_period)
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return Environment(ref_period)
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return Environment()
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def switch_clock(self, external):
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self._write(struct.pack(
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@ -140,8 +135,6 @@ class CommGeneric:
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self._write(struct.pack(">B", ord(c)))
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logger.debug("running kernel: %s", kname)
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def _receive_rpc_values(self):
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r = []
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while True:
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@ -47,19 +47,15 @@ def _no_debug_unparse(label, node):
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class Core(AutoDB):
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class DBKeys:
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comm = Device()
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external_clock = Parameter(None)
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ref_period = Argument()
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external_clock = Argument(False)
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def build(self):
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self.runtime_env = self.comm.get_runtime_env()
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self.core = self
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self.comm.core = self
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if self.external_clock is None:
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self.ref_period = self.runtime_env.internal_ref_period
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self.comm.switch_clock(False)
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else:
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self.ref_period = 1/self.external_clock
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self.comm.switch_clock(True)
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self.comm.switch_clock(self.external_clock)
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self.initial_time = int64(self.runtime_env.warmup_time/self.ref_period)
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def transform_stack(self, func_def, rpc_map, exception_map,
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@ -190,9 +190,8 @@ def _debug_dump_obj(obj):
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class Environment(LinkInterface):
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def __init__(self, internal_ref_period):
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def __init__(self):
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self.cpu_type = "or1k"
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self.internal_ref_period = internal_ref_period
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# allow 1ms for all initial DDS programming
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self.warmup_time = 1*units.ms
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@ -203,5 +202,4 @@ class Environment(LinkInterface):
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return obj
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def __repr__(self):
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return "<Environment {} {}>".format(self.cpu_type,
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str(1/self.ref_period))
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return "<Environment {}>".format(self.cpu_type)
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@ -1,5 +1,3 @@
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from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.misc import optree
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@ -255,13 +253,6 @@ class Channel:
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self.ififo_depth = ififo_depth
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class _CSRs(AutoCSR):
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def __init__(self):
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self.frequency_i = CSRStatus(32)
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self.frequency_fn = CSRStatus(8)
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self.frequency_fd = CSRStatus(8)
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class _KernelCSRs(AutoCSR):
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def __init__(self, chan_sel_width,
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data_width, address_width, full_ts_width):
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@ -300,7 +291,6 @@ class RTIO(Module):
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for c in channels)
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# CSRs
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self.csrs = _CSRs()
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self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
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data_width, address_width,
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counter_width + fine_ts_width)
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@ -405,18 +395,5 @@ class RTIO(Module):
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<< fine_ts_width)
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)
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# Frequency CSRs
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clk_freq = Fraction(clk_freq).limit_denominator(255)
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clk_freq_i = int(clk_freq)
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clk_freq_f = clk_freq - clk_freq_i
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self.comb += [
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self.csrs.frequency_i.status.eq(clk_freq_i),
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self.csrs.frequency_fn.status.eq(clk_freq_f.numerator),
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self.csrs.frequency_fd.status.eq(clk_freq_f.denominator)
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]
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def get_csrs(self):
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return self.csrs.get_csrs()
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def get_kernel_csrs(self):
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return self.kcsrs.get_csrs()
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@ -9,7 +9,7 @@
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {}
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"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
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},
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"pmt0": {
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@ -9,7 +9,7 @@
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {}
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"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
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},
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"pmt0": {
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@ -178,16 +178,6 @@ void comm_serve(object_loader load_object, kernel_runner run_kernel)
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if(msgtype == MSGTYPE_REQUEST_IDENT) {
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send_char(MSGTYPE_IDENT);
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send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
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#ifdef ARTIQ_AMP
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#warning TODO
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send_int(125*1000*1000);
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send_char(0);
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send_char(1);
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#else
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send_int(rtio_frequency_i_read());
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send_char(rtio_frequency_fn_read());
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send_char(rtio_frequency_fd_read());
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#endif
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} else if(msgtype == MSGTYPE_LOAD_OBJECT)
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receive_and_load_object(load_object);
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else if(msgtype == MSGTYPE_RUN_KERNEL)
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@ -98,7 +98,7 @@ class UP(_Peripherals):
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def __init__(self, *args, **kwargs):
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_Peripherals.__init__(self, *args, **kwargs)
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rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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@ -127,7 +127,7 @@ class AMP(_Peripherals):
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
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self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
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rtio_csrs = self.rtio.get_kernel_csrs()
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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@ -125,7 +125,7 @@ class UP(_Peripherals):
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def __init__(self, platform, **kwargs):
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_Peripherals.__init__(self, platform, **kwargs)
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rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
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@ -158,7 +158,7 @@ class AMP(_Peripherals):
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self.add_memory_region("mailbox",
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self.mem_map["mailbox"] + 0x80000000, 4)
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rtio_csrs = self.rtio.get_kernel_csrs()
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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@ -112,7 +112,7 @@ class UP(BaseSoC):
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clk_freq=125000000,
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counter_width=32)
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rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,
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