forked from M-Labs/artiq
targets/kc705: do not depend on particular Migen generated signal names
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@ -75,11 +75,11 @@ class _Peripherals(MiniSoC):
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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platform.add_platform_command("""
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create_clock -name rsys_clk -period 8.0 [get_nets rsys_clk]
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create_clock -name rio_clk -period 8.0 [get_nets rio_clk]
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create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
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create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
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set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""")
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""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
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class UP(_Peripherals):
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def __init__(self, *args, **kwargs):
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