forked from M-Labs/artiq
soc: support QC2 and AD9914 (untested)
This commit is contained in:
parent
b6310b72db
commit
944bfafefa
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@ -6,15 +6,14 @@ from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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class AD9858(Module):
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"""Wishbone interface to the AD9858 DDS chip.
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class AD9xxx(Module):
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"""Wishbone interface to the AD9858 and AD9914 DDS chips.
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Addresses 0-63 map the AD9858 registers.
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Data is zero-padded.
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Addresses 0-2**flen(pads.a)-1 map the AD9xxx registers.
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Write to address 64 to pulse the FUD signal.
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Address 65 is a GPIO register that controls the sel, p and reset signals.
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sel is mapped to the lower bits, followed by p and reset.
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Write to address 2**flen(pads.a) to pulse the FUD signal.
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Address 2**flen(pads.a)+1 is a GPIO register that controls the
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sel and reset signals. sel is mapped to the lower bits, followed by reset.
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Write timing:
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Address is set one cycle before assertion of we_n.
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@ -28,6 +27,7 @@ class AD9858(Module):
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Design:
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All IO pads are registered.
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With QC1 adapter:
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LVDS driver/receiver propagation delays are 3.6+4.5 ns max
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LVDS state transition delays are 20, 15 ns max
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Schmitt trigger delays are 6.4ns max
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@ -38,15 +38,15 @@ class AD9858(Module):
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read_wait_cycles=10, hiz_wait_cycles=3,
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bus=None):
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if bus is None:
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bus = wishbone.Interface(data_width=8)
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bus = wishbone.Interface(data_width=flen(pads.d))
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self.bus = bus
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# # #
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dts = TSTriple(8)
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dts = TSTriple(flen(pads.d))
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self.specials += dts.get_tristate(pads.d)
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hold_address = Signal()
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dr = Signal(8)
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dr = Signal(flen(pads.d))
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rx = Signal()
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self.sync += [
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If(~hold_address, pads.a.eq(bus.adr)),
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@ -55,13 +55,14 @@ class AD9858(Module):
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dts.oe.eq(~rx)
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]
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gpio = Signal(flen(pads.sel) + flen(pads.p) + 1)
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gpio = Signal(flen(pads.sel) + 1)
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gpio_load = Signal()
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self.sync += If(gpio_load, gpio.eq(bus.dat_w))
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self.comb += [
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Cat(pads.sel, pads.p).eq(gpio),
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pads.rst_n.eq(~gpio[-1]),
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]
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self.comb += pads.sel.eq(gpio),
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if hasattr(pads, "rst"):
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self.comb += pads.rst.eq(gpio[-1])
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else:
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self.comb += pads.rst_n.eq(~gpio[-1])
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bus_r_gpio = Signal()
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self.comb += If(bus_r_gpio,
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@ -71,7 +72,10 @@ class AD9858(Module):
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)
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fud = Signal()
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self.sync += pads.fud_n.eq(~fud)
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if hasattr(pads, "fud"):
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self.sync += pads.fud.eq(fud)
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else:
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self.sync += pads.fud_n.eq(~fud)
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pads.wr_n.reset = 1
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pads.rd_n.reset = 1
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@ -87,7 +91,7 @@ class AD9858(Module):
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fsm.act("IDLE",
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If(bus.cyc & bus.stb,
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If(bus.adr[6],
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If(bus.adr[flen(pads.a)],
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If(bus.adr[0],
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NextState("GPIO")
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).Else(
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@ -168,7 +172,6 @@ class _TestPads:
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self.a = Signal(6)
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self.d = Signal(8)
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self.sel = Signal(5)
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self.p = Signal(2)
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self.fud_n = Signal()
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self.wr_n = Signal()
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self.rd_n = Signal()
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@ -178,11 +181,11 @@ class _TestPads:
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class _TB(Module):
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def __init__(self):
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pads = _TestPads()
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self.submodules.dut = AD9858(pads, drive_fud=True)
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self.submodules.dut = AD9xxx(pads, drive_fud=True)
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self.submodules.initiator = wishbone.Initiator(_test_gen())
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(
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self.initiator.bus, self.dut.bus)
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if __name__ == "__main__":
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run_simulation(_TB(), vcd_name="ad9858.vcd")
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run_simulation(_TB(), vcd_name="ad9xxx.vcd")
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@ -1,5 +1,6 @@
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from mibuild.generic_platform import *
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fmc_adapter_io = [
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("ttl", 0, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
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@ -28,10 +29,10 @@ fmc_adapter_io = [
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Subsignal("sel", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
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"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
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"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
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Subsignal("fud_n", Pins("LPC:LA21_N")),
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Subsignal("fud", Pins("LPC:LA21_N")),
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Subsignal("wr_n", Pins("LPC:LA24_P")),
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Subsignal("rd_n", Pins("LPC:LA25_N")),
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Subsignal("rst_in", Pins("LPC:LA25_P")),
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Subsignal("rst", Pins("LPC:LA25_P")),
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IOStandard("LVTTL")),
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("i2c", 0,
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@ -1,14 +1,14 @@
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from migen.fhdl.std import *
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from artiq.gateware import ad9858 as ad9858_ll
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from artiq.gateware import ad9xxx
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class AD9858(Module):
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def __init__(self, pads, nchannels=8, **kwargs):
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class _AD9xxx(Module):
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def __init__(self, ftw_base, pads, nchannels, **kwargs):
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self.submodules._ll = RenameClockDomains(
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ad9858_ll.AD9858(pads, **kwargs), "rio")
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self.submodules._rt2wb = RT2WB(7, self._ll.bus)
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ad9xxx.AD9xxx(pads, **kwargs), "rio")
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self.submodules._rt2wb = RT2WB(flen(pads.a)+1, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = [Signal(32) for i in range(nchannels)]
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@ -16,21 +16,44 @@ class AD9858(Module):
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# keep track of the currently selected channel
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current_channel = Signal(max=nchannels)
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self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 65),
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current_channel.eq(self.rtlink.o.data))
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self.sync.rio += If(self.rtlink.o.stb &
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(self.rtlink.o.address == 2**flen(pads.a)+1),
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current_channel.eq(self.rtlink.o.data))
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# keep track of frequency tuning words, before they are FUDed
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ftws = [Signal(32) for i in range(nchannels)]
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for c, ftw in enumerate(ftws):
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for i in range(4):
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self.sync.rio += \
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If(self.rtlink.o.stb & \
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(self.rtlink.o.address == 0x0a+i) & \
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(current_channel == c),
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ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
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)
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if flen(pads.d) == 8:
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for i in range(4):
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self.sync.rio += \
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If(self.rtlink.o.stb & \
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(self.rtlink.o.address == ftw_base+i) & \
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(current_channel == c),
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ftw[i*8:(i+1)*8].eq(self.rtlink.o.data)
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)
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elif flen(pads.d) == 16:
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for i in range(2):
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self.sync.rio += \
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If(self.rtlink.o.stb & \
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(self.rtlink.o.address == ftw_base+2*i) & \
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(current_channel == c),
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ftw[i*16:(i+1)*16].eq(self.rtlink.o.data)
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)
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else:
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raise NotImplementedError
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# FTW to probe on FUD
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws)):
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fud = self.rtlink.o.stb & (self.rtlink.o.address == 64)
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fud = self.rtlink.o.stb & \
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(self.rtlink.o.address == 2**flen(pads.a))
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self.sync.rio += If(fud & (current_channel == c), probe.eq(ftw))
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class AD9858(_AD9xxx):
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def __init__(self, pads, nchannels, **kwargs):
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_AD9xxx.__init__(self, 0x0a, pads, nchannels, **kwargs)
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class AD9914(_AD9xxx):
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def __init__(self, pads, nchannels, **kwargs):
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_AD9xxx.__init__(self, 0x2d, pads, nchannels, **kwargs)
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@ -40,7 +40,7 @@ void dds_init(long long int timestamp, int channel)
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now = timestamp - DURATION_INIT;
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(DDS_GPIO, channel | (1 << 7));
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DDS_WRITE(DDS_GPIO, channel | (1 << 5));
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DDS_WRITE(DDS_GPIO, channel);
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DDS_WRITE(0x00, 0x78);
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@ -10,7 +10,7 @@ from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.kc705 import MiniSoC
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware import rtio, nist_qc1, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, dds
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@ -32,7 +32,7 @@ class _RTIOCRG(Module, AutoCSR):
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o_O=self.cd_rtio.clk)
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class NIST_QC1(MiniSoC, AMPSoC):
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class _NIST_QCx(MiniSoC, AMPSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 13,
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@ -52,18 +52,44 @@ class NIST_QC1(MiniSoC, AMPSoC):
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sdram_controller_settings=MiniconSettings(l2_size=128*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.pll_sys)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.add_platform_command("""
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create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
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create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
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set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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rtio_csrs)
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class NIST_QC1(_NIST_QCx):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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_NIST_QCx.__init__(self, platform, cpu_type, **kwargs)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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# RTIO channels
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rtio_channels = []
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for i in range(2):
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phy = ttl_simple.Inout(platform.request("pmt", i))
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@ -81,35 +107,46 @@ class NIST_QC1(MiniSoC, AMPSoC):
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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self.add_constant("DDS_AD9858")
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.add_rtio(rtio_channels)
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# RTIO core
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self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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if isinstance(platform.toolchain, XilinxVivadoToolchain):
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platform.add_platform_command("""
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create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
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create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
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set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
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class NIST_QC2(_NIST_QCx):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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_NIST_QCx.__init__(self, platform, cpu_type, **kwargs)
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platform.add_extension(nist_qc2.fmc_adapter_io)
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# CPU connections
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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rtio_csrs)
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rtio_channels = []
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for i in range(16):
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if i % 4 == 3:
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phy = ttl_simple.Inout(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 11)
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self.add_constant("DDS_AD9914")
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self.add_constant("DDS_ONEHOT_SEL")
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phy = dds.AD9914(platform.request("dds"), 11)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.add_rtio(rtio_channels)
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default_subtarget = NIST_QC1
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@ -118,7 +118,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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phy = dds.AD9858(platform.request("dds"))
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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