Sebastien Bourdeauducq
bfacd1e5b3
eem: fix Grabber cc_0-2 signal definitions
2021-02-07 18:01:05 +08:00
Sebastien Bourdeauducq
f7a33a1f99
gateware: make 7-series EEM handling functions shareable
2021-02-07 14:34:26 +08:00
Harry Ho
a0fd5261ea
kc705: cleanup
2021-01-22 11:11:13 +08:00
Harry Ho
7c4eed7a11
kc705: simplify DRTIO master & satellite
...
* KC705 master: user can no longer choose whether or not the SMA acts as the 2nd DRTIO channel; SFP and SMA now act as the 1st and 2nd channel respectively by default.
* KC705 satellite: user should now use `--sma` to enable using the SMA as the satellite channel; SFP acts as the satellite channel by default.
2021-01-22 11:11:13 +08:00
Harry Ho
88b14082b6
drtio/transceiver/gtx: delete obsolete modules
2021-01-20 15:05:32 +08:00
Harry Ho
9daf77bd58
kc705: add multichannel support on satellite
...
* Two DRTIO channels (i.e. satellite and repeater) are enabled by default.
* User can choose either the SFP or SMA as the satellite channel (by passing `--drtio-sat sfp` or --drtio-sat sma` to the argparser), and the unchosen would become the repeater channel.
2021-01-20 15:05:32 +08:00
Harry Ho
52afd4ef6b
kc705: add GTX multilane support, add multichannel support on master
...
* One DRTIO master channel is enabled by default.
* User can set the SMA as the 2nd master channel (by passing --drtio-sma to the argparser).
* Multi-channel (i.e. with repeaters) on KC705 satellite is supported but has not been implemented yet.
2021-01-20 15:05:32 +08:00
Harry Ho
f6d39fd6ba
kc705: revive DRTIO master with updated syntax
...
* KC705 master variant now uses Si5324 as synthesiser.
* Multi-channel has not been implemented yet.
2021-01-20 15:05:31 +08:00
Harry Ho
f25e86e934
kc705: revive DRTIO satellite with updated syntax, update GTX
...
* Multi-channel has not been implemented yet.
2021-01-20 11:25:38 +08:00
Sebastien Bourdeauducq
c675488a99
reorganize JSON schema files
2021-01-16 10:43:14 +08:00
Astro
c6807f4594
kasli_generic: validate description against schema, use defaults from schema
2021-01-16 10:35:23 +08:00
Astro
45b5cfce05
gateware: add a kasli_generic.schema.json
2021-01-16 10:35:23 +08:00
Harry Ho
cff7bcc122
Merge branch 'master' ( 43be383c86
) into k7-drtio
2020-12-31 13:30:46 +08:00
Harry Ho
dc7addf394
Revert "drtio: remove KC705/GTX support"
...
This reverts commit ebdbaaad32
.
2020-12-31 13:29:50 +08:00
Harry Ho
43ecb3fea6
sayma: add comments about CPLL line rate on KU GTH
2020-12-19 17:05:20 +08:00
Harry Ho
8cd794e9f4
jesd204_tools: use new syntax from jesd204b core
...
* requires jesd204b changes as in https://github.com/HarryMakes/jesd204b/tree/gth
2020-12-19 17:05:20 +08:00
Sebastien Bourdeauducq
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
Sebastien Bourdeauducq
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
Robert Jördens
a9dd0a268c
Merge pull request #1533 from m-labs/phaser
...
Phaser
2020-10-19 09:30:12 +02:00
Robert Jördens
30d1acee9f
fastlink: fix fastino style link
2020-10-18 20:43:21 +00:00
Robert Jördens
d98357051c
add ref data
2020-10-18 20:43:21 +00:00
Robert Jördens
139385a571
fastlink: add fastino test
2020-10-18 17:11:09 +00:00
Sebastien Bourdeauducq
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
Sebastien Bourdeauducq
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
hartytp
a058be2ede
wrpll: fix test_helper_collector
2020-10-08 19:43:12 +08:00
Sebastien Bourdeauducq
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
Sebastien Bourdeauducq
07d43b6e5f
wrpll: babysit Vivado DSP retiming
...
Design now passes timing.
2020-10-08 17:51:27 +08:00
Sebastien Bourdeauducq
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
Sebastien Bourdeauducq
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
Sebastien Bourdeauducq
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
...
We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
...
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
...
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
Robert Jördens
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
Robert Jördens
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
Sebastien Bourdeauducq
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
Robert Jördens
868a9a1f0c
phaser: new multidds
2020-09-16 14:06:38 +00:00
Robert Jördens
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
Robert Jördens
fdd2d6f2fb
phaser: SI methods
2020-09-12 11:02:37 +00:00
Robert Jördens
4e24700205
phaser: spelling
2020-09-09 16:52:52 +00:00
Robert Jördens
8aaeaa604e
phaser: share_lut
2020-09-07 16:06:35 +00:00
Astro
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
Harry Ho
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
Harry Ho
1ad9deaf91
fmcdio_vhdci_eem: fix pin naming
2020-08-31 16:21:45 +08:00
Astro
45ae6202c0
build_soc: add identifier_str override option
...
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
Robert Jördens
272dc5d36a
phaser: documentation
2020-08-28 16:36:44 +00:00
Robert Jördens
96fc248d7c
phaser: synchronize multidds to frame
2020-08-27 14:28:19 +00:00
Robert Jördens
c10ac2c92a
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
2020-08-27 14:26:09 +00:00
Robert Jördens
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
Robert Jördens
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
Robert Jördens
20fcfd95e9
phaser: coredevice shim, readback fix
2020-08-24 15:46:31 +00:00
Robert Jördens
bcefb06e19
phaser: ddb template, split crc
2020-08-24 14:51:50 +00:00
Robert Jördens
11c9def589
phaser: readback delay, test fastlink
2020-08-24 14:49:36 +00:00
Robert Jördens
63e4b95325
fastlink: rework crc injection
2020-08-23 19:41:13 +00:00
Robert Jördens
a27a03ab3c
fastlink: fix crc vs data width
2020-08-23 19:02:50 +00:00
Robert Jördens
7e584d0da1
fastino: use fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
3e99f1ce5a
phaser: refactor link
2020-08-22 11:56:23 +00:00
Robert Jördens
a34a647ec4
phaser: refactor fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
Sebastien Bourdeauducq
504f72a02c
rtio: remove legacy i_overflow_reset CSR
2020-08-06 17:52:32 +08:00
cw-mlabs
e4b16428f5
wrpll: fix run signal
2020-07-27 13:02:02 +08:00
cw-mlabs
8dd9a6d024
wrpll: fix scl signal
2020-07-27 12:59:32 +08:00
Sebastien Bourdeauducq
4340a5cfc1
rtio/dma: fix previous commit
2020-07-12 10:14:22 +08:00
Sebastien Bourdeauducq
f2e0d27334
rtio/dma: remove dead/broken code
2020-07-12 10:13:18 +08:00
Sebastien Bourdeauducq
901be75ba4
sayma_rtm: fix Si5324 reset
...
Closes #1483
2020-07-11 09:51:01 +08:00
Sebastien Bourdeauducq
2d1f1fff7f
kasli_generic: do not attempt to use SFP LED for RTIO on 2.0+
2020-07-08 18:14:44 +08:00
Sebastien Bourdeauducq
cb76f9da89
metlino: fix CSR collisions
...
Closes #1425
2020-05-29 15:59:44 +08:00
Sebastien Bourdeauducq
bd9eec15c0
metlino: increase number of DRTIO links
...
Seems OK with Vivado 2019.2.
2020-05-29 15:59:16 +08:00
Sebastien Bourdeauducq
d8b5bcf019
sayma_amc: support uTCA backplane for DRTIO
2020-05-29 14:58:49 +08:00
Sebastien Bourdeauducq
8b939b7cb3
sayma_amc: remove Master (obsoleted by Metlino)
2020-05-29 14:40:49 +08:00
Sebastien Bourdeauducq
4e9a529e5a
kasli: integrate WRPLL
2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq
60e5f1c18e
kasli: DRTIO support for Kasli 2
2020-05-07 20:09:43 +08:00
Sebastien Bourdeauducq
1f2182d4c7
kasli: default to hardware v2
2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq
b83afedf43
kasli: light up ERROR LED on panic
2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq
7e400a78f4
kasli: compile tester for hw 2.0 by default
2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq
3a7819704a
rtio: support direct 64-bit now CSR in KernelInitiator
2020-04-26 16:04:32 +08:00
Sebastien Bourdeauducq
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
Robert Jördens
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
Sebastien Bourdeauducq
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
Sebastien Bourdeauducq
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
Sebastien Bourdeauducq
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
Sebastien Bourdeauducq
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
Robert Jördens
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
Sebastien Bourdeauducq
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
Sebastien Bourdeauducq
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
Sebastien Bourdeauducq
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
Sebastien Bourdeauducq
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
Robert Jördens
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00