mirror of https://github.com/m-labs/artiq
wrpll: document DDMTD collector and fix unwrapping
hartytp
parent
7c2519c912
commit
ebb7ccbfd1
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@ -130,61 +130,180 @@ class DDMTD(Module, AutoCSR):
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class Collector(Module):
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def __init__(self, N):
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self.tag_helper = Signal((N, True))
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self.tag_helper_update = Signal()
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self.tag_main = Signal((N, True))
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self.tag_main_update = Signal()
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""" Generates loop filter inputs from DDMTD outputs.
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self.output = Signal((N + 1, True))
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When the WR PLL is locked, the following ideally (no noise etc) obtain:
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- f_main = f_ref
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- f_helper = f_ref * (2^N-1) / 2^N
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- f_beat = f_ref - f_helper = f_ref / 2^N (cycle time is: dt=1/f_beat)
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- the reference and main DCXO tags are equal each cycle
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- the reference and main DCXO tags decrease by 1 each cycle (the tag
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difference is f_helper*dt = f_helper/f_beat = (2^N-1) so we are 1 tag
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away from a complete wrap around of the N-bit DDMTD counter)
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Since the main and reference tags cycle through all possible values when
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locked, we need to unwrap the collector outputs to avoid glitches
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(particularly noise around transitions). Currently we do this in hardware,
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but we should consider extending the processor to allow us to do it
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inside the filters at a later stage (at which point, the collector
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essentially becomes a the trigger for the loop filters).
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The input to the main DCXO lock loop filter is the difference between the
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reference and main tags after phase unwrapping.
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The input to the helper DCXO lock loop filter is the difference between the
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current reference tag and the previous reference tag plus 1, after
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phase unwrapping.
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"""
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def __init__(self, N):
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self.ref_stb = Signal()
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self.main_stb = Signal()
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self.tag_ref = Signal(N)
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self.tag_main = Signal(N)
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self.out_stb = Signal()
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self.out_main = Signal((N+2, True))
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self.out_helper = Signal((N+2, True))
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self.out_tag_ref = Signal(N)
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self.out_tag_main = Signal(N)
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tag_ref_r = Signal(N)
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tag_main_r = Signal(N)
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main_tag_diff = Signal((N+2, True))
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helper_tag_diff = Signal((N+2, True))
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# # #
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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tag_collector = Signal((N + 1, True))
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fsm.act("IDLE",
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If(self.tag_main_update & self.tag_helper_update,
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NextValue(tag_collector, 0),
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NextState("UPDATE")
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).Elif(self.tag_main_update,
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NextValue(tag_collector, self.tag_main),
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NextState("WAITHELPER")
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).Elif(self.tag_helper_update,
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NextValue(tag_collector, -self.tag_helper),
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NextValue(self.out_stb, 0),
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If(self.ref_stb & self.main_stb,
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NextValue(tag_ref_r, self.tag_ref),
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NextValue(tag_main_r, self.tag_main),
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NextState("DIFF")
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).Elif(self.ref_stb,
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NextValue(tag_ref_r, self.tag_ref),
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NextState("WAITMAIN")
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).Elif(self.main_stb,
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NextValue(tag_main_r, self.tag_main),
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NextState("WAITREF")
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)
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)
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fsm.act("WAITHELPER",
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If(self.tag_helper_update,
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NextValue(tag_collector, tag_collector - self.tag_helper),
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NextState("LEADCHECK")
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fsm.act("WAITREF",
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If(self.ref_stb,
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NextValue(tag_ref_r, self.tag_ref),
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NextState("DIFF")
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)
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)
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fsm.act("WAITMAIN",
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If(self.tag_main_update,
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NextValue(tag_collector, tag_collector + self.tag_main),
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NextState("LAGCHECK")
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If(self.main_stb,
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NextValue(tag_main_r, self.tag_main),
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NextState("DIFF")
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)
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)
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# To compensate DDMTD counter roll-over when main is ahead of roll-over
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# and helper is after roll-over
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fsm.act("LEADCHECK",
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If(tag_collector > 0,
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NextValue(tag_collector, tag_collector - (2**N - 1))
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),
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NextState("UPDATE")
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fsm.act("DIFF",
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NextValue(main_tag_diff, tag_main_r - tag_ref_r),
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NextValue(helper_tag_diff, tag_ref_r - self.out_tag_ref + 1),
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NextState("UNWRAP")
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)
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# To compensate DDMTD counter roll-over when helper is ahead of roll-over
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# and main is after roll-over
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fsm.act("LAGCHECK",
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If(tag_collector < 0,
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NextValue(tag_collector, tag_collector + (2**N - 1))
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fsm.act("UNWRAP",
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If(main_tag_diff - self.out_main > 2**(N-1),
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NextValue(main_tag_diff, main_tag_diff - 2**N)
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).Elif(self.out_main - main_tag_diff > 2**(N-1),
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NextValue(main_tag_diff, main_tag_diff + 2**N)
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),
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NextState("UPDATE")
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If(helper_tag_diff - self.out_helper > 2**(N-1),
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NextValue(helper_tag_diff, helper_tag_diff - 2**N)
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).Elif(self.out_helper - helper_tag_diff > 2**(N-1),
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NextValue(helper_tag_diff, helper_tag_diff + 2**N)
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),
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NextState("OUTPUT")
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)
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fsm.act("UPDATE",
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NextValue(self.output, tag_collector),
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fsm.act("OUTPUT",
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NextValue(self.out_tag_ref, tag_ref_r),
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NextValue(self.out_tag_main, tag_main_r),
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NextValue(self.out_main, main_tag_diff),
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NextValue(self.out_helper, helper_tag_diff),
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NextValue(self.out_stb, 1),
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NextState("IDLE")
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)
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def test_collector_main():
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N = 2
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collector = Collector(N=N)
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# check collector phase unwrapping
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tags = [(0, 0, 0),
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(0, 1, 1),
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(2, 1, -1),
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(3, 1, -2),
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(0, 1, -3),
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(1, 1, -4),
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(2, 1, -5),
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(3, 1, -6),
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(3, 3, -4),
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(0, 0, -4),
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(0, 1, -3),
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(0, 2, -2),
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(0, 3, -1),
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(0, 0, 0)]
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for i in range(10):
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tags.append((i % (2**N), (i+1) % (2**N), 1))
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def generator():
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for tag_ref, tag_main, out in tags:
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yield collector.tag_ref.eq(tag_ref)
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yield collector.tag_main.eq(tag_main)
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yield collector.main_stb.eq(1)
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yield collector.ref_stb.eq(1)
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yield
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yield collector.main_stb.eq(0)
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yield collector.ref_stb.eq(0)
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while not (yield collector.out_stb):
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yield
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out_main = yield collector.out_main
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assert out_main == out
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run_simulation(collector, generator())
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def test_collector_helper():
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N = 3
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collector = Collector(N=N)
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# check collector phase unwrapping
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tags = [((2**N - 1 - tag) % (2**N), 0) for tag in range(20)]
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tags += [((tags[-1][0] + 1 + tag) % (2**N), 2) for tag in range(20)]
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tags += [((tags[-1][0] - 2 - 2*tag) % (2**N), -1) for tag in range(20)]
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def generator():
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for tag_ref, out in tags:
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yield collector.tag_ref.eq(tag_ref)
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yield collector.main_stb.eq(1)
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yield collector.ref_stb.eq(1)
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yield
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yield collector.main_stb.eq(0)
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yield collector.ref_stb.eq(0)
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while not (yield collector.out_stb):
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yield
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out_helper = yield collector.out_helper
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assert out_helper == out
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run_simulation(collector, generator())
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if __name__ == "__main__":
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test_collector_main()
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test_collector_helper()
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