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metlino: increase number of DRTIO links 

Seems OK with Vivado 2019.2.
pull/1450/head^2
Sebastien Bourdeauducq 2020-05-29 15:59:16 +08:00
parent d5c1eaa16e
commit bd9eec15c0
1 changed files with 1 additions and 2 deletions
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3
artiq/gateware/targets/metlino.py
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@ -67,8 +67,7 @@ class Master(MiniSoC, AMPSoC):
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean", 0),
# use only a few channels to work around Vivado bug
data_pads=[platform.request("mch_fabric_d", i) for i in range(3)],
data_pads=[platform.request("mch_fabric_d", i) for i in range(11)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")