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phaser: coredevice shim, readback fix
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parent
bcefb06e19
commit
20fcfd95e9
45
artiq/coredevice/phaser.py
Normal file
45
artiq/coredevice/phaser.py
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@ -0,0 +1,45 @@
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from artiq.language.core import kernel, portable, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us
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from artiq.language.types import TInt32, TList, TFloat
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PHASER_ADDR_BOARD_ID = 0x00
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PHASER_BOARD_ID = 19
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class Phaser:
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kernel_invariants = {"core", "channel_base"}
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def __init__(self, dmgr, channel_base, readback_delay=1,
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core_device="core"):
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self.channel_base = channel_base << 8
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self.core = dmgr.get(core_device)
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self.readback_delay = readback_delay
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@kernel
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def init(self):
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board_id = self.read(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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@kernel
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def write(self, addr, data):
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"""Write data to a Fastino register.
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output(self.channel_base | addr | 0x80, data)
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@kernel
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def read(self, addr):
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"""Read from Fastino register.
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TODO: untested
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:param addr: Address to read from.
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:return: The data read.
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"""
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rtio_output(self.channel_base | addr, 0)
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response = rtio_input_data(self.channel_base >> 8)
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return response >> self.readback_delay
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@ -491,7 +491,10 @@ class PeripheralManager:
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"type": "local",
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"module": "artiq.coredevice.phaser",
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"class": "Phaser",
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"arguments": {{"channel": 0x{channel:06x}}}
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"arguments": {{
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"channel_base": 0x{channel:06x},
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"readback_delay": 1,
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}}
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}}""",
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name=self.get_name("phaser"),
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channel=rtio_offset)
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@ -86,6 +86,9 @@ class SerDes(Module):
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self.crcb.data.eq(Cat([sri[-2] for sri in sr[::-1]])),
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self.crcb.last.eq(self.crca.next),
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miso_sr_next.eq(Cat(self.data[-1], miso_sr)),
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# unload miso
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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]
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self.sync.rio_phy += [
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# shift everything by two bits
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@ -101,9 +104,6 @@ class SerDes(Module):
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self.crca.last.eq(0),
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# transpose, load
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[sri.eq(Cat(words[i::n_mosi])) for i, sri in enumerate(sr)],
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# unload miso
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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# inject crc for the last cycle
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crc_insert.eq(self.crca.next if n_crc // n_mosi == 1
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else self.crcb.next),
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@ -32,8 +32,7 @@ class Phaser(Module):
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n_channels = 2
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n_samples = 8
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n_bits = 14
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body = [[(Signal(n_bits), Signal(n_bits))
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for i in range(n_channels)] for j in range(n_samples)]
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body = [Signal(n_bits) for i in range(n_channels*n_samples*2)]
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assert len(Cat(header.raw_bits(), body)) == \
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len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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