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wrpll: style

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This commit is contained in:
Sebastien Bourdeauducq 2020-10-08 15:00:49 +08:00
parent ebb7ccbfd1
commit 17c952b8fb
1 changed files with 2 additions and 3 deletions
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5
artiq/gateware/drtio/wrpll/ddmtd.py
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@ -130,7 +130,7 @@ class DDMTD(Module, AutoCSR):
class Collector(Module):
""" Generates loop filter inputs from DDMTD outputs.
"""Generates loop filter inputs from DDMTD outputs.
When the WR PLL is locked, the following ideally (no noise etc) obtain:
- f_main = f_ref
@ -234,7 +234,6 @@ class Collector(Module):
def test_collector_main():
N = 2
collector = Collector(N=N)
# check collector phase unwrapping
@ -277,7 +276,6 @@ def test_collector_main():
def test_collector_helper():
N = 3
collector = Collector(N=N)
# check collector phase unwrapping
@ -304,6 +302,7 @@ def test_collector_helper():
run_simulation(collector, generator())
if __name__ == "__main__":
test_collector_main()
test_collector_helper()